ADC_CTRL Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.420s	5.854ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.270s	759.221us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.140s	313.250us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.233m	27.341ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.290s	1.020ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.470s	469.081us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.140s	313.250us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	1.020ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.941m	331.009ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	6.918m	482.359ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	9.194m	320.816ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	7.015m	497.166ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.226m	179.465ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	4.400m	614.642ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	14.516m	511.083ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.410m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.860s	3.343ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	58.580s	38.563ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.064m	102.009ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	3.578m	266.354ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.620s	529.240us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.010s	302.519us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.360s	881.718us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.360s	881.718us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.270s	759.221us	1	1	100.00
		adc_ctrl_csr_rw	1.140s	313.250us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	1.020ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.370s	2.240ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.270s	759.221us	1	1	100.00
		adc_ctrl_csr_rw	1.140s	313.250us	1	1	100.00
		adc_ctrl_csr_aliasing	2.290s	1.020ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.370s	2.240ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	4.630s	3.796ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.650s	4.458ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.650s	4.458ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.790s	13.587ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.55715064615917691082982564462444083593751930889881668645930119966493820754012
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---