AES/MASKED Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	236.024us	1	1	100.00
V1	smoke	aes_smoke	4.000s	283.555us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	57.360us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	120.454us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	3.000s	121.277us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	83.790us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	75.169us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	120.454us	1	1	100.00
		aes_csr_aliasing	3.000s	83.790us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	4.000s	283.555us	1	1	100.00
		aes_config_error	3.000s	110.155us	1	1	100.00
		aes_stress	7.000s	1.563ms	1	1	100.00
V2	key_length	aes_smoke	4.000s	283.555us	1	1	100.00
		aes_config_error	3.000s	110.155us	1	1	100.00
		aes_stress	7.000s	1.563ms	1	1	100.00
V2	back2back	aes_stress	7.000s	1.563ms	1	1	100.00
		aes_b2b	11.000s	466.629us	1	1	100.00
V2	backpressure	aes_stress	7.000s	1.563ms	1	1	100.00
V2	multi_message	aes_smoke	4.000s	283.555us	1	1	100.00
		aes_config_error	3.000s	110.155us	1	1	100.00
		aes_stress	7.000s	1.563ms	1	1	100.00
		aes_alert_reset	3.000s	98.200us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	86.431us	1	1	100.00
		aes_config_error	3.000s	110.155us	1	1	100.00
		aes_alert_reset	3.000s	98.200us	1	1	100.00
V2	trigger_clear_test	aes_clear	8.000s	1.077ms	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	494.098us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	98.200us	1	1	100.00
V2	stress	aes_stress	7.000s	1.563ms	1	1	100.00
V2	sideload	aes_stress	7.000s	1.563ms	1	1	100.00
		aes_sideload	5.000s	459.576us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	358.142us	1	1	100.00
V2	stress_all	aes_stress_all	1.583m	4.810ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	212.357us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	83.708us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	83.708us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	57.360us	1	1	100.00
		aes_csr_rw	2.000s	120.454us	1	1	100.00
		aes_csr_aliasing	3.000s	83.790us	1	1	100.00
		aes_same_csr_outstanding	3.000s	105.788us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	57.360us	1	1	100.00
		aes_csr_rw	2.000s	120.454us	1	1	100.00
		aes_csr_aliasing	3.000s	83.790us	1	1	100.00
		aes_same_csr_outstanding	3.000s	105.788us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	4.000s	194.921us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	127.185us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.390ms	1	1	100.00
		aes_tl_intg_err	3.000s	217.796us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	217.796us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	98.200us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	283.555us	1	1	100.00
		aes_stress	7.000s	1.563ms	1	1	100.00
		aes_alert_reset	3.000s	98.200us	1	1	100.00
		aes_core_fi	2.000s	90.357us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	182.092us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	98.086us	1	1	100.00
		aes_stress	7.000s	1.563ms	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	1.563ms	1	1	100.00
		aes_sideload	5.000s	459.576us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	98.086us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	98.086us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	98.086us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	98.086us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	98.086us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	1.563ms	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	1.563ms	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	155.968us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	155.968us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	3.000s	111.455us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	155.968us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	98.200us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	1.000s	63.161us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	155.968us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	111.455us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.000s	721.471us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.64832321355536831552205005883583935884646036185072654451489023552203557271254
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.97665138081999879200596018829372094118256472311022478073099276094881996407849
      Line 212, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 721471194 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 721471194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---