| V1 |
smoke |
aon_timer_smoke |
1.300s |
725.975us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.110s |
710.526us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
1.060s |
378.785us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
1.900s |
629.804us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
0.910s |
763.314us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
0.940s |
274.023us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
1.060s |
378.785us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.910s |
763.314us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
0.770s |
284.981us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
1.020s |
460.957us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
0.850s |
557.547us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
1.160s |
526.608us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
3.222m |
163.073ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.960s |
456.272us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.920s |
273.182us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.850s |
459.587us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.850s |
459.587us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.110s |
710.526us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.060s |
378.785us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.910s |
763.314us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.160s |
2.479ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.110s |
710.526us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.060s |
378.785us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
0.910s |
763.314us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.160s |
2.479ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
10.880s |
7.792ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
11.630s |
8.425ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
11.630s |
8.425ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.760s |
522.571us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.010s |
658.393us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
2.220s |
3.988ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.680s |
576.047us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
3.200s |
3.974ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
9.910s |
6.822ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |