EDN Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.980s 47.955us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.880s 62.018us 1 1 100.00
V1 csr_rw edn_csr_rw 0.860s 27.433us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.830s 508.981us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.080s 35.638us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.020s 24.005us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.860s 27.433us 1 1 100.00
edn_csr_aliasing 1.080s 35.638us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.070s 37.079us 1 1 100.00
V2 csrng_commands edn_genbits 1.070s 37.079us 1 1 100.00
V2 genbits edn_genbits 1.070s 37.079us 1 1 100.00
V2 interrupts edn_intr 1.090s 22.506us 1 1 100.00
V2 alerts edn_alert 1.250s 33.080us 1 1 100.00
V2 errs edn_err 1.030s 27.594us 1 1 100.00
V2 disable edn_disable 0.940s 37.113us 1 1 100.00
edn_disable_auto_req_mode 1.030s 92.689us 1 1 100.00
V2 stress_all edn_stress_all 1.320s 55.860us 1 1 100.00
V2 intr_test edn_intr_test 0.710s 52.706us 1 1 100.00
V2 alert_test edn_alert_test 0.950s 28.026us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.900s 101.383us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.900s 101.383us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.880s 62.018us 1 1 100.00
edn_csr_rw 0.860s 27.433us 1 1 100.00
edn_csr_aliasing 1.080s 35.638us 1 1 100.00
edn_same_csr_outstanding 1.000s 67.834us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.880s 62.018us 1 1 100.00
edn_csr_rw 0.860s 27.433us 1 1 100.00
edn_csr_aliasing 1.080s 35.638us 1 1 100.00
edn_same_csr_outstanding 1.000s 67.834us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.570s 1.067ms 1 1 100.00
edn_tl_intg_err 1.970s 318.141us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 19.157us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.250s 33.080us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.570s 1.067ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.570s 1.067ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.570s 1.067ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.570s 1.067ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.250s 33.080us 1 1 100.00
edn_sec_cm 6.570s 1.067ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.250s 33.080us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.970s 318.141us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets