HMAC Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.330s 303.437us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.960s 37.639us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.790s 20.310us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.530s 2.320ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.510s 1.407ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.738m 28.628ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.790s 20.310us 1 1 100.00
hmac_csr_aliasing 4.510s 1.407ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 41.600s 1.067ms 1 1 100.00
V2 back_pressure hmac_back_pressure 10.770s 991.634us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.583m 7.252ms 1 1 100.00
hmac_test_sha384_vectors 5.486m 10.566ms 1 1 100.00
hmac_test_sha512_vectors 23.510s 2.125ms 1 1 100.00
hmac_test_hmac256_vectors 6.870s 455.870us 1 1 100.00
hmac_test_hmac384_vectors 9.940s 331.059us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1.099ms 1 1 100.00
V2 burst_wr hmac_burst_wr 22.780s 21.047ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 26.690s 1.129ms 1 1 100.00
V2 error hmac_error 20.760s 1.832ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 24.850s 1.530ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.330s 303.437us 1 1 100.00
hmac_long_msg 41.600s 1.067ms 1 1 100.00
hmac_back_pressure 10.770s 991.634us 1 1 100.00
hmac_datapath_stress 26.690s 1.129ms 1 1 100.00
hmac_burst_wr 22.780s 21.047ms 1 1 100.00
hmac_stress_all 9.249m 59.009ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.330s 303.437us 1 1 100.00
hmac_long_msg 41.600s 1.067ms 1 1 100.00
hmac_back_pressure 10.770s 991.634us 1 1 100.00
hmac_datapath_stress 26.690s 1.129ms 1 1 100.00
hmac_wipe_secret 24.850s 1.530ms 1 1 100.00
hmac_test_sha256_vectors 3.583m 7.252ms 1 1 100.00
hmac_test_sha384_vectors 5.486m 10.566ms 1 1 100.00
hmac_test_sha512_vectors 23.510s 2.125ms 1 1 100.00
hmac_test_hmac256_vectors 6.870s 455.870us 1 1 100.00
hmac_test_hmac384_vectors 9.940s 331.059us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1.099ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.330s 303.437us 1 1 100.00
hmac_long_msg 41.600s 1.067ms 1 1 100.00
hmac_back_pressure 10.770s 991.634us 1 1 100.00
hmac_datapath_stress 26.690s 1.129ms 1 1 100.00
hmac_burst_wr 22.780s 21.047ms 1 1 100.00
hmac_error 20.760s 1.832ms 1 1 100.00
hmac_wipe_secret 24.850s 1.530ms 1 1 100.00
hmac_test_sha256_vectors 3.583m 7.252ms 1 1 100.00
hmac_test_sha384_vectors 5.486m 10.566ms 1 1 100.00
hmac_test_sha512_vectors 23.510s 2.125ms 1 1 100.00
hmac_test_hmac256_vectors 6.870s 455.870us 1 1 100.00
hmac_test_hmac384_vectors 9.940s 331.059us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1.099ms 1 1 100.00
hmac_stress_all 9.249m 59.009ms 1 1 100.00
V2 stress_all hmac_stress_all 9.249m 59.009ms 1 1 100.00
V2 alert_test hmac_alert_test 0.760s 37.748us 1 1 100.00
V2 intr_test hmac_intr_test 0.720s 41.551us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.760s 145.182us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.760s 145.182us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.960s 37.639us 1 1 100.00
hmac_csr_rw 0.790s 20.310us 1 1 100.00
hmac_csr_aliasing 4.510s 1.407ms 1 1 100.00
hmac_same_csr_outstanding 1.630s 45.514us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.960s 37.639us 1 1 100.00
hmac_csr_rw 0.790s 20.310us 1 1 100.00
hmac_csr_aliasing 4.510s 1.407ms 1 1 100.00
hmac_same_csr_outstanding 1.630s 45.514us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.800s 215.162us 1 1 100.00
hmac_tl_intg_err 1.790s 101.885us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.790s 101.885us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.330s 303.437us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.280s 1.417ms 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.907m 16.853ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.710s 91.147us 1 1 100.00
TOTAL 28 28 100.00