I2C Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: `b8fc3df`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	59.290s	6.308ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	23.650s	1.071ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.880s	57.232us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.850s	28.866us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.270s	191.932us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.820s	223.117us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.890s	155.701us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.850s	28.866us	1	1	100.00
		i2c_csr_aliasing	1.820s	223.117us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.970s	410.177us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.457m	29.664ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	32.960s	9.760ms	1	1	100.00
V2	host_override	i2c_host_override	0.970s	48.379us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.277m	4.248ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.130s	1.653ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.040s	195.415us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.970s	304.740us	1	1	100.00
		i2c_host_fifo_reset_rx	2.740s	575.892us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	53.890s	5.252ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.520s	521.025us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.010s	88.931us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.870s	465.998us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	21.480s	27.696ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.930s	847.997us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.960s	1.346ms	1	1	100.00
		i2c_target_intr_smoke	7.090s	1.684ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.910s	405.255us	1	1	100.00
		i2c_target_fifo_reset_tx	1.220s	220.835us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.190s	12.723ms	1	1	100.00
		i2c_target_stress_rd	8.960s	1.346ms	1	1	100.00
		i2c_target_intr_stress_wr	4.376m	22.173ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.750s	2.338ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	7.400s	4.104ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.410s	2.245ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	18.150s	10.147ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.920s	2.721ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.450s	1.209ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	32.960s	9.760ms	1	1	100.00
		i2c_host_perf_precise	10.871m	23.247ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.520s	521.025us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.640s	139.518us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.200s	583.384us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.730s	479.535us	1	1	100.00
		i2c_target_nack_txstretch	1.290s	150.706us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.040s	3.952ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.770s	1.354ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.740s	30.011us	1	1	100.00
V2	intr_test	i2c_intr_test	0.680s	48.530us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.540s	220.898us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.540s	220.898us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.880s	57.232us	1	1	100.00
		i2c_csr_rw	0.850s	28.866us	1	1	100.00
		i2c_csr_aliasing	1.820s	223.117us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	151.789us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.880s	57.232us	1	1	100.00
		i2c_csr_rw	0.850s	28.866us	1	1	100.00
		i2c_csr_aliasing	1.820s	223.117us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	151.789us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	1.410s	190.731us	1	1	100.00
		i2c_sec_cm	0.870s	473.770us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.410s	190.731us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	39.030s	5.454ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.780s	46.747us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.390s	3.046ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

Test i2c_host_error_intr has 1 failures.

0.i2c_host_error_intr.38810450679764615019693229198717670842504828347139328098440045547403949751859
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 410176645 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 410176645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.95027490140721820579029382115808442837022450257324621594351532108248177943914
Line 134, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 29664082199 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 29664082199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 1 failures.
- 0.i2c_target_stress_all_with_rand_reset.111273539303435912390123923776304659646828978194179959054213707298270711531430
  Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3045536079 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 3045536079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.112952782111200147853708470945301414368280802445400464570209852766037438230329
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  88930976 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  88930976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.32562429725819362510408801322357485786464582482320154588128269149989586111324
    Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 465997757 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 465997757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.65440057668655000687213468486756319140564432770009724457621287275313955942879
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  46746959 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  46746959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.71972050813637720563631209374063450555819643845171798121186843831719915416929
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10147338719 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10147338719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.44891008599323025265447952107083163038398263787343469880174840807163346894084
    Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5454363366 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5454363366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.113695760413833887027074974255280030628216539569310110307450500884673940288805
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 150705905 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 150705905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```