KEYMGR Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.730s	277.599us	1	1	100.00
V1	random	keymgr_random	32.810s	4.751ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.800s	245.471us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.910s	59.386us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.730s	1.464ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.420s	380.927us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	0.990s	120.899us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.910s	59.386us	1	1	100.00
		keymgr_csr_aliasing	4.420s	380.927us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	4.860s	139.212us	1	1	100.00
V2	sideload	keymgr_sideload	2.680s	85.570us	1	1	100.00
		keymgr_sideload_kmac	4.890s	859.964us	1	1	100.00
		keymgr_sideload_aes	1.860s	37.443us	1	1	100.00
		keymgr_sideload_otbn	2.310s	63.520us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.840s	426.851us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.430s	242.014us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.020s	132.811us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	25.070s	11.986ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.960s	87.410us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.930s	67.404us	1	1	100.00
V2	stress_all	keymgr_stress_all	8.290s	888.747us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.750s	23.522us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.750s	30.959us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.770s	49.348us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.770s	49.348us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.800s	245.471us	1	1	100.00
		keymgr_csr_rw	0.910s	59.386us	1	1	100.00
		keymgr_csr_aliasing	4.420s	380.927us	1	1	100.00
		keymgr_same_csr_outstanding	1.800s	108.801us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.800s	245.471us	1	1	100.00
		keymgr_csr_rw	0.910s	59.386us	1	1	100.00
		keymgr_csr_aliasing	4.420s	380.927us	1	1	100.00
		keymgr_same_csr_outstanding	1.800s	108.801us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
		keymgr_tl_intg_err	4.820s	3.352ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.080s	87.441us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.080s	87.441us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.080s	87.441us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.080s	87.441us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.500s	446.359us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.820s	3.352ms	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.080s	87.441us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.860s	139.212us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	32.810s	4.751ms	1	1	100.00
		keymgr_csr_rw	0.910s	59.386us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	32.810s	4.751ms	1	1	100.00
		keymgr_csr_rw	0.910s	59.386us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	32.810s	4.751ms	1	1	100.00
		keymgr_csr_rw	0.910s	59.386us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.430s	242.014us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.960s	87.410us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.960s	87.410us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	32.810s	4.751ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.550s	97.553us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.620s	61.026us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.430s	242.014us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.620s	61.026us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.620s	61.026us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.620s	61.026us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.180s	4.357ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.620s	61.026us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.010s	187.443us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.93688627744353795252074619642986960744663490521971192840395947317779975069602
      Line 450, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 187442964 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 187442964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---