| V1 |
smoke |
kmac_smoke |
20.340s |
1.402ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.850s |
39.955us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.110s |
42.464us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
7.020s |
2.312ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
5.490s |
264.133us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.060s |
76.483us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.110s |
42.464us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.490s |
264.133us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.960s |
40.126us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.480s |
112.706us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
7.879m |
95.995ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
14.682m |
29.617ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
30.880s |
8.462ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
36.030s |
15.547ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
22.928m |
86.970ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
17.360m |
87.086ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
39.678m |
106.804ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
32.010m |
85.773ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.920s |
317.944us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.980s |
334.512us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.930m |
38.316ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.920m |
45.224ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
1.999m |
15.871ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
3.434m |
20.437ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
3.196m |
10.831ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
7.270s |
1.216ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.160s |
61.761us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.610s |
420.129us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.410s |
27.865us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
21.460s |
13.677ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
3.350s |
145.907us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
15.241m |
14.075ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.800s |
17.400us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.900s |
50.058us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.270s |
290.744us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.270s |
290.744us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.850s |
39.955us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.110s |
42.464us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.490s |
264.133us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.530s |
29.007us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.850s |
39.955us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.110s |
42.464us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.490s |
264.133us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.530s |
29.007us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.650s |
249.687us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.650s |
249.687us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.650s |
249.687us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.650s |
249.687us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.410s |
303.241us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
29.250s |
2.272ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
2.220s |
97.972us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
2.220s |
97.972us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
3.350s |
145.907us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
20.340s |
1.402ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.930m |
38.316ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.650s |
249.687us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
29.250s |
2.272ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
29.250s |
2.272ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
29.250s |
2.272ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
20.340s |
1.402ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
3.350s |
145.907us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
29.250s |
2.272ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
1.946m |
5.453ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
20.340s |
1.402ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.260m |
2.972ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |