OTBN Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 9.000s 42.274us 0 1 0.00
V1 single_binary otbn_single 5.000s 11.995us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 28.519us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 36.957us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 98.388us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 20.017us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 6.000s 42.891us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 36.957us 1 1 100.00
otbn_csr_aliasing 3.000s 20.017us 1 1 100.00
V1 mem_walk otbn_mem_walk 29.000s 11.164ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 328.319us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 31.000s 154.853us 0 1 0.00
V2 multi_error otbn_multi_err 41.000s 173.564us 0 1 0.00
V2 back_to_back otbn_multi 52.000s 188.006us 0 1 0.00
V2 stress_all otbn_stress_all 1.783m 404.430us 0 1 0.00
V2 lc_escalation otbn_escalate 12.000s 52.510us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 4.000s 22.591us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 315.918us 0 1 0.00
V2 alert_test otbn_alert_test 4.000s 13.667us 1 1 100.00
V2 intr_test otbn_intr_test 4.000s 31.707us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 7.000s 90.066us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 7.000s 90.066us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 28.519us 1 1 100.00
otbn_csr_rw 4.000s 36.957us 1 1 100.00
otbn_csr_aliasing 3.000s 20.017us 1 1 100.00
otbn_same_csr_outstanding 4.000s 385.410us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 28.519us 1 1 100.00
otbn_csr_rw 4.000s 36.957us 1 1 100.00
otbn_csr_aliasing 3.000s 20.017us 1 1 100.00
otbn_same_csr_outstanding 4.000s 385.410us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 9.000s 19.724us 0 1 0.00
otbn_dmem_err 9.000s 36.624us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 39.000s 170.224us 0 1 0.00
otbn_controller_ispr_rdata_err 6.000s 25.287us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 101.258us 0 1 0.00
otbn_urnd_err 9.000s 49.891us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 42.889us 0 1 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 5.000s 43.122us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 15.335us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.383m 3.620ms 1 1 100.00
otbn_tl_intg_err 16.000s 136.113us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 48.000s 296.567us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 9.000s 42.274us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 36.624us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 19.724us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 16.000s 136.113us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 12.000s 52.510us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 19.724us 0 1 0.00
otbn_dmem_err 9.000s 36.624us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 22.591us 1 1 100.00
otbn_illegal_mem_acc 7.000s 42.889us 0 1 0.00
otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 19.724us 0 1 0.00
otbn_dmem_err 9.000s 36.624us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 22.591us 1 1 100.00
otbn_illegal_mem_acc 7.000s 42.889us 0 1 0.00
otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 12.000s 52.510us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 19.724us 0 1 0.00
otbn_dmem_err 9.000s 36.624us 0 1 0.00
otbn_zero_state_err_urnd 4.000s 22.591us 1 1 100.00
otbn_illegal_mem_acc 7.000s 42.889us 0 1 0.00
otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 5.000s 180.542us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 31.413us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 47.000s 243.599us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 47.000s 243.599us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 5.000s 39.552us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 8.000s 601.613us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 119.857us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 119.857us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 50.301us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 52.000s 188.006us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 44.953us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 5.000s 11.995us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.383m 3.620ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.767m 1.079ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets