PATTGEN Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: `b8fc3df`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	217.527us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	25.378us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	14.995us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	316.687us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	14.773us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	41.873us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	14.995us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.773us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	12.000s	1.323ms	1	1	100.00
V2	error	pattgen_error	1.000s	285.955us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	19.794us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	21.773us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	435.501us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	435.501us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	25.378us	1	1	100.00
		pattgen_csr_rw	1.000s	14.995us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.773us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	58.949us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	25.378us	1	1	100.00
		pattgen_csr_rw	1.000s	14.995us	1	1	100.00
		pattgen_csr_aliasing	2.000s	14.773us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	58.949us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	56.984us	1	1	100.00
		pattgen_sec_cm	2.000s	230.526us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	56.984us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	10.000s	4.536ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	2.000s	72.776us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

Job timed out after * minutes has 2 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.99943110833864100648223059251668711227490338176208863173424654314013447897437
    Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.77164693084713383966521015616745314828417443079349146791120159643115513380521
    Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  Job timed out after 180 minutes
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.48127984056151558271079790097480702444113632535265913478174443026776228478220
Line 118, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1806317845 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1806335680 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1806335680 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1806615680 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]