ROM_CTRL/32KB Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.410s	1.355ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.030s	577.236us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.480s	388.001us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.800s	131.372us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.080s	170.948us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.450s	159.065us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.480s	388.001us	1	1	100.00
		rom_ctrl_csr_aliasing	7.080s	170.948us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.730s	347.298us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.220s	372.797us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.280s	587.365us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	11.630s	341.794us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.830s	741.392us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.560s	128.028us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.320s	557.120us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.320s	557.120us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.030s	577.236us	1	1	100.00
		rom_ctrl_csr_rw	4.480s	388.001us	1	1	100.00
		rom_ctrl_csr_aliasing	7.080s	170.948us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.310s	865.337us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.030s	577.236us	1	1	100.00
		rom_ctrl_csr_rw	4.480s	388.001us	1	1	100.00
		rom_ctrl_csr_aliasing	7.080s	170.948us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.310s	865.337us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	21.580s	1.548ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
		rom_ctrl_tl_intg_err	26.570s	845.650us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.410s	1.355ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.410s	1.355ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.410s	1.355ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	26.570s	845.650us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
		rom_ctrl_kmac_err_chk	7.830s	741.392us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	36.680s	1.838ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	21.580s	1.548ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.692m	560.845us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.320s	180.245us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.100324103730060184082945289771766634760970654390878616999449578419380046697776
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 2646364ps failed at 2646364ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 2646364ps failed at 2646364ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'