RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: `b8fc3df`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.170s	937.830us	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	0.900s	169.827us	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.090s	585.652us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	5.150s	3.216ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.960s	268.798us	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	4.580s	3.986ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	6.710s	4.643ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	10.040s	5.442ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.149m	135.493ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.460s	761.870us	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.980s	173.318us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.120s	664.228us	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.000s	106.459us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.990s	251.588us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.990s	1.853ms	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.930s	456.437us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.190s	1.434ms	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.460s	761.870us	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.110s	471.673us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.950s	708.441us	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.120s	664.228us	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.790s	81.311us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.220s	77.844us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	1.670s	235.071us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	19.760s	5.031ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	19.090s	2.334ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	0.910s	34.666us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	19.090s	2.334ms	1	1	100.00
		rv_dm_csr_rw	1.670s	235.071us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	0.880s	59.286us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.730s	53.013us	1	1	100.00
V1		TOTAL			26	27	96.30
V2	idcode	rv_dm_smoke	1.170s	937.830us	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.910s	185.792us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.610s	403.934us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.840s	123.995us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	4.100s	1.867ms	1	1	100.00
V2	sba	rv_dm_sba_tl_access	3.787m	300.000ms	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	5.552m	300.000ms	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	2.695m	300.000ms	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.997m	300.000ms	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.190s	642.268us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.390s	3.511ms	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.990s	297.452us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.080s	78.035us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.690s	12.459ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.070s	22.325us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.870s	358.125us	1	1	100.00
V2	stress_all	rv_dm_stress_all	2.990s	3.953ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.680s	41.168us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	4.360s	615.883us	1	1	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	4.360s	615.883us	1	1	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	19.090s	2.334ms	1	1	100.00
		rv_dm_csr_hw_reset	1.220s	77.844us	1	1	100.00
		rv_dm_csr_rw	1.670s	235.071us	1	1	100.00
		rv_dm_same_csr_outstanding	6.290s	1.135ms	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	19.090s	2.334ms	1	1	100.00
		rv_dm_csr_hw_reset	1.220s	77.844us	1	1	100.00
		rv_dm_csr_rw	1.670s	235.071us	1	1	100.00
		rv_dm_same_csr_outstanding	6.290s	1.135ms	1	1	100.00
V2		TOTAL			13	19	68.42
V2S	tl_intg_err	rv_dm_sec_cm	1.490s	701.866us	1	1	100.00
		rv_dm_tl_intg_err	7.060s	944.432us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	7.060s	944.432us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.390s	3.511ms	1	1	100.00
		rv_dm_debug_disabled	1.190s	128.782us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	2.390s	3.511ms	1	1	100.00
		rv_dm_debug_disabled	1.190s	128.782us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.170s	937.830us	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.980s	525.192us	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.860s	45.278us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.860s	45.278us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.980s	525.192us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.790s	69.585us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.660s	17.786us	1	1	100.00
		TOTAL			45	53	84.91

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.874122805350784594077585080731637188201931279398999271642040250645191923511
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.2589367406043111143518014957161127218668826469680019888326595251364556088115
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.97662536998506364767582255702928879414908832982485753263858414932373221982292
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.81487338603015790683584936795431816787742887311583111920483382916965683455318
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.18941116410899166339129763810792197017626893753955721367195718059334382543499
    Line 94, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 638
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6076) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.70081900456414662994752846444412661964495178151226878440021506280643927401
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  22324878 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6076) { a_addr: 'he0727514  a_data: 'h5a108774  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha6  a_opcode: 'h4  a_user: 'h1a236  d_param: 'h0  d_source: 'ha6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  22324878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5744) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.69281265884549195503042982679077699497579933472375196756569878150751554220370
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  69584909 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@5744) { a_addr: 'hc630e6a8  a_data: 'h2d81e818  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8f  a_opcode: 'h4  a_user: 'h1ba3d  d_param: 'h0  d_source: 'h8f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  69584909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@9052) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

0.rv_dm_csr_mem_rw_with_rand_reset.47224337955698815283555179874750772376152205623852464996478791640886741998951
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  34666256 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@9052) { a_addr: 'h4f040530  a_data: 'h3e284696  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h79  a_opcode: 'h4  a_user: 'h19249  d_param: 'h0  d_source: 'h79  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  34666256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---