RV_TIMER Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.940s	206.869us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.590s	16.218us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.880s	13.546us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.430s	406.972us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.870s	15.807us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.980s	373.303us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.880s	13.546us	1	1	100.00
		rv_timer_csr_aliasing	0.870s	15.807us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.710s	152.548us	0	1	0.00
V2	disabled	rv_timer_disabled	1.090s	513.822us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	0.920s	690.194us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	0.920s	690.194us	1	1	100.00
V2	stress	rv_timer_stress_all	3.920s	11.447ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.800s	15.795us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.630s	18.952us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.340s	173.912us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.340s	173.912us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.590s	16.218us	1	1	100.00
		rv_timer_csr_rw	0.880s	13.546us	1	1	100.00
		rv_timer_csr_aliasing	0.870s	15.807us	1	1	100.00
		rv_timer_same_csr_outstanding	0.740s	63.203us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.590s	16.218us	1	1	100.00
		rv_timer_csr_rw	0.880s	13.546us	1	1	100.00
		rv_timer_csr_aliasing	0.870s	15.807us	1	1	100.00
		rv_timer_same_csr_outstanding	0.740s	63.203us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.850s	106.526us	1	1	100.00
		rv_timer_tl_intg_err	1.270s	447.041us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.270s	447.041us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.930s	241.902us	0	1	0.00
V3	max_value	rv_timer_max	0.780s	45.135us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.690s	3.400ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.57584858248409209618102899755140413015044754689355609049011849687397533861450
      Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 241901553 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5c258104) == 0x1
        UVM_INFO @ 241901553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.63337044058261262512029545119964043412147226905712191312872042160226190612724
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 152548042 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x78eaa904) == 0x1
        UVM_INFO @ 152548042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.41057954863993629650217305114750172839021330114963521985264271756424228212616
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45134947 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45134947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---