| V1 |
smoke |
spi_device_flash_and_tpm |
37.020s |
3.894ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_device_csr_hw_reset |
1.230s |
146.974us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_device_csr_rw |
1.100s |
111.639us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_device_csr_bit_bash |
17.200s |
1.579ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_device_csr_aliasing |
14.830s |
1.247ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_device_csr_mem_rw_with_rand_reset |
2.060s |
184.369us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_device_csr_rw |
1.100s |
111.639us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
14.830s |
1.247ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_device_mem_walk |
0.680s |
10.112us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_device_mem_partial_access |
1.480s |
89.364us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
csb_read |
spi_device_csb_read |
0.780s |
36.466us |
1 |
1 |
100.00 |
| V2 |
mem_parity |
spi_device_mem_parity |
1.030s |
45.817us |
1 |
1 |
100.00 |
| V2 |
mem_cfg |
spi_device_ram_cfg |
0.950s |
19.540us |
1 |
1 |
100.00 |
| V2 |
tpm_read |
spi_device_tpm_rw |
1.340s |
108.477us |
1 |
1 |
100.00 |
| V2 |
tpm_write |
spi_device_tpm_rw |
1.340s |
108.477us |
1 |
1 |
100.00 |
| V2 |
tpm_hw_reg |
spi_device_tpm_read_hw_reg |
11.930s |
24.425ms |
1 |
1 |
100.00 |
|
|
spi_device_tpm_sts_read |
0.830s |
117.764us |
1 |
1 |
100.00 |
| V2 |
tpm_fully_random_case |
spi_device_tpm_all |
12.660s |
14.681ms |
1 |
1 |
100.00 |
| V2 |
pass_cmd_filtering |
spi_device_pass_cmd_filtering |
1.920s |
33.809us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
pass_addr_translation |
spi_device_pass_addr_payload_swap |
4.410s |
5.143ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
pass_payload_translation |
spi_device_pass_addr_payload_swap |
4.410s |
5.143ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_info_slots |
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_status |
spi_device_intercept |
5.810s |
1.487ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_jedec |
spi_device_intercept |
5.810s |
1.487ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_sfdp |
spi_device_intercept |
5.810s |
1.487ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_fast_read |
spi_device_intercept |
5.810s |
1.487ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_pipeline |
spi_device_intercept |
5.810s |
1.487ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
flash_cmd_upload |
spi_device_upload |
24.230s |
82.704ms |
1 |
1 |
100.00 |
| V2 |
mailbox_command |
spi_device_mailbox |
14.890s |
6.267ms |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_outside_command |
spi_device_mailbox |
14.890s |
6.267ms |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_inside_command |
spi_device_mailbox |
14.890s |
6.267ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_buffer |
spi_device_flash_mode |
23.320s |
2.331ms |
1 |
1 |
100.00 |
|
|
spi_device_read_buffer_direct |
3.390s |
124.246us |
1 |
1 |
100.00 |
| V2 |
cmd_dummy_cycle |
spi_device_mailbox |
14.890s |
6.267ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
quad_spi |
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
dual_spi |
spi_device_flash_all |
59.810s |
14.965ms |
1 |
1 |
100.00 |
| V2 |
4b_3b_feature |
spi_device_cfg_cmd |
3.360s |
190.444us |
1 |
1 |
100.00 |
| V2 |
write_enable_disable |
spi_device_cfg_cmd |
3.360s |
190.444us |
1 |
1 |
100.00 |
| V2 |
TPM_with_flash_or_passthrough_mode |
spi_device_flash_and_tpm |
37.020s |
3.894ms |
1 |
1 |
100.00 |
| V2 |
tpm_and_flash_trans_with_min_inactive_time |
spi_device_flash_and_tpm_min_idle |
21.520s |
3.127ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_device_stress_all |
4.869m |
192.849ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_device_alert_test |
0.690s |
43.708us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_device_intr_test |
0.720s |
71.850us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_device_tl_errors |
3.440s |
67.062us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_device_tl_errors |
3.440s |
67.062us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_device_csr_hw_reset |
1.230s |
146.974us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.100s |
111.639us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
14.830s |
1.247ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
2.090s |
80.002us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_device_csr_hw_reset |
1.230s |
146.974us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
1.100s |
111.639us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
14.830s |
1.247ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
2.090s |
80.002us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
22 |
22 |
100.00 |
| V2S |
tl_intg_err |
spi_device_sec_cm |
1.120s |
124.865us |
1 |
1 |
100.00 |
|
|
spi_device_tl_intg_err |
8.910s |
784.363us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_device_tl_intg_err |
8.910s |
784.363us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_device_flash_mode_ignore_cmds |
11.600s |
2.222ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
33 |
33 |
100.00 |