SRAM_CTRL/RET Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.660s	750.219us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	22.171us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	14.636us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.530s	975.134us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.640s	52.283us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.840s	28.940us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	14.636us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	52.283us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.870s	1.324ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.710s	157.379us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	14.930m	71.425ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.669m	5.930ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	33.130s	6.060ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.283m	903.899us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.370s	3.378ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.278m	10.713ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.330s	99.525us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.970m	14.844ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.840s	113.537us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.680s	420.593us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.070s	260.199us	1	1	100.00
V2	regwen	sram_ctrl_regwen	48.180s	997.327us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.720s	130.407us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.002m	91.540ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.670s	37.495us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.530s	72.547us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.530s	72.547us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	22.171us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	14.636us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	52.283us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.740s	12.548us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	22.171us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	14.636us	1	1	100.00
		sram_ctrl_csr_aliasing	0.640s	52.283us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.740s	12.548us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.160s	396.925us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
		sram_ctrl_tl_intg_err	1.880s	769.255us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.880s	769.255us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	48.180s	997.327us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	48.180s	997.327us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	14.636us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.278m	10.713ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.278m	10.713ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.278m	10.713ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.370s	3.378ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.820s	71.070us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.160s	396.925us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.860s	33.542us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.660s	750.219us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.660s	750.219us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.278m	10.713ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.370s	3.378ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.660s	750.219us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.710s	2.234us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.170s	991.370us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.104443732246915474261688450688057878255817524476672563089485544475886928036188
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2234210 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2234210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---