SYSRST_CTRL Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.580s 2.111ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.410s 2.471ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.020s 2.207ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.110s 2.301ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 12.300s 6.013ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.270s 2.047ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.200m 39.034ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.420s 3.987ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.470s 2.065ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.270s 2.047ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 3.987ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.391m 90.342ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 2.517m 99.654ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.870s 3.485ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.620s 2.776ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.020s 2.514ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.990s 2.253ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 5.830s 3.825ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 5.220s 2.612ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.300s 10.472ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.256m 39.341ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 8.360s 16.326ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.300s 2.023ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.190s 2.062ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.930s 2.143ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.930s 2.143ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 12.300s 6.013ms 1 1 100.00
sysrst_ctrl_csr_rw 3.270s 2.047ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 3.987ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.190s 10.579ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 12.300s 6.013ms 1 1 100.00
sysrst_ctrl_csr_rw 3.270s 2.047ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.420s 3.987ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 21.190s 10.579ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 19.080s 42.144ms 1 1 100.00
sysrst_ctrl_tl_intg_err 25.160s 22.320ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 25.160s 22.320ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.980s 18.802ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00