UART Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: b8fc3df

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	12.090s	11.066ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	28.512us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.790s	23.446us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.490s	361.168us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.640s	22.235us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.000s	32.722us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.790s	23.446us	1	1	100.00
		uart_csr_aliasing	0.640s	22.235us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	6.660s	12.592ms	1	1	100.00
V2	parity	uart_smoke	12.090s	11.066ms	1	1	100.00
		uart_tx_rx	6.660s	12.592ms	1	1	100.00
V2	parity_error	uart_intr	32.520s	48.098ms	1	1	100.00
		uart_rx_parity_err	36.190s	120.739ms	1	1	100.00
V2	watermark	uart_tx_rx	6.660s	12.592ms	1	1	100.00
		uart_intr	32.520s	48.098ms	1	1	100.00
V2	fifo_full	uart_fifo_full	29.470s	49.523ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.308m	109.074ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	31.910s	251.361ms	1	1	100.00
V2	rx_frame_err	uart_intr	32.520s	48.098ms	1	1	100.00
V2	rx_break_err	uart_intr	32.520s	48.098ms	1	1	100.00
V2	rx_timeout	uart_intr	32.520s	48.098ms	1	1	100.00
V2	perf	uart_perf	1.246m	9.362ms	1	1	100.00
V2	sys_loopback	uart_loopback	9.270s	12.741ms	1	1	100.00
V2	line_loopback	uart_loopback	9.270s	12.741ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	4.210s	8.826ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.380s	3.516ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.220s	804.007us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.140s	2.424ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.653m	123.012ms	1	1	100.00
V2	stress_all	uart_stress_all	2.920m	315.396ms	1	1	100.00
V2	alert_test	uart_alert_test	0.620s	18.068us	1	1	100.00
V2	intr_test	uart_intr_test	0.550s	20.973us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.660s	59.209us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.660s	59.209us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	28.512us	1	1	100.00
		uart_csr_rw	0.790s	23.446us	1	1	100.00
		uart_csr_aliasing	0.640s	22.235us	1	1	100.00
		uart_same_csr_outstanding	0.940s	25.049us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	28.512us	1	1	100.00
		uart_csr_rw	0.790s	23.446us	1	1	100.00
		uart_csr_aliasing	0.640s	22.235us	1	1	100.00
		uart_same_csr_outstanding	0.940s	25.049us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.120s	247.340us	1	1	100.00
		uart_tl_intg_err	1.110s	196.783us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.110s	196.783us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.190s	20.092ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.101285444998685790526527957430722699513560993458828276475098761583625920283608
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3201911295 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 3201956750 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 3202002205 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 3202047660 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 3202093115 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata