CHIP Simulation Results

Monday October 13 2025 17:20:49 UTC

GitHub Revision: `b8fc3df`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.664m	3.162ms	1	1	100.00
		chip_sw_example_rom	1.338m	2.423ms	1	1	100.00
		chip_sw_example_manufacturer	2.428m	2.373ms	1	1	100.00
		chip_sw_example_concurrency	2.314m	3.145ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.082m	4.196ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.412m	6.301ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.824m	6.102ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.131h	36.635ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	44.920s	2.484ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.131h	36.635ms	1	1	100.00
		chip_csr_rw	6.412m	6.301ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.450s	215.002us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.010m	3.954ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.010m	3.954ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.010m	3.954ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.485m	4.663ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.485m	4.663ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.323m	4.745ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.703m	3.862ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.162m	4.503ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.361m	8.560ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.945m	8.100ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.760m	4.442ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.529m	5.653ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.529m	5.653ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.230m	3.485ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.633m	2.881ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.668m	4.085ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.052m	11.568ms	1	1	100.00
		chip_tap_straps_testunlock0	5.334m	6.453ms	1	1	100.00
		chip_tap_straps_rma	1.266m	2.570ms	1	1	100.00
		chip_tap_straps_prod	1.561m	3.141ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.697m	3.386ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.571m	9.177ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.725m	6.219ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.725m	6.219ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.226m	7.852ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	21.315m	14.727ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.162m	4.046ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.853m	6.244ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.007m	19.185ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.030m	2.808ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	14.173m	7.222ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.242m	3.091ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.707m	7.588ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.269m	3.213ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.039m	4.929ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.741m	2.949ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.862m	3.007ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.040m	6.349ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.366m	5.438ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.410m	2.782ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.366m	5.438ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.359m	3.490ms	1	1	100.00
		chip_sw_aes_smoketest	2.552m	2.596ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.268m	2.935ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.861m	2.795ms	1	1	100.00
		chip_sw_csrng_smoketest	2.477m	2.845ms	1	1	100.00
		chip_sw_entropy_src_smoketest	15.974m	7.640ms	1	1	100.00
		chip_sw_gpio_smoketest	3.499m	3.616ms	1	1	100.00
		chip_sw_hmac_smoketest	2.665m	2.788ms	1	1	100.00
		chip_sw_kmac_smoketest	3.034m	3.499ms	1	1	100.00
		chip_sw_otbn_smoketest	14.029m	6.940ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.609m	5.749ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.027m	5.681ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.376m	3.142ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.719m	3.508ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.926m	2.713ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.955m	2.647ms	1	1	100.00
		chip_sw_uart_smoketest	2.281m	3.300ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.388m	2.939ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.038m	6.002ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.168h	60.579ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.142m	15.076ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.102m	4.751ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.392m	2.914ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.889m	2.931ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.967h	53.796ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.091h	56.473ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.080m	2.860ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.080m	2.860ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.131h	36.635ms	1	1	100.00
		chip_same_csr_outstanding	19.330m	16.227ms	1	1	100.00
		chip_csr_hw_reset	2.082m	4.196ms	1	1	100.00
		chip_csr_rw	6.412m	6.301ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.131h	36.635ms	1	1	100.00
		chip_same_csr_outstanding	19.330m	16.227ms	1	1	100.00
		chip_csr_hw_reset	2.082m	4.196ms	1	1	100.00
		chip_csr_rw	6.412m	6.301ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.480s	579.157us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.290s	53.912us	1	1	100.00
		xbar_smoke_large_delays	44.380s	7.221ms	1	1	100.00
		xbar_smoke_slow_rsp	34.330s	3.829ms	1	1	100.00
		xbar_random_zero_delays	21.110s	363.089us	1	1	100.00
		xbar_random_large_delays	5.211m	49.903ms	1	1	100.00
		xbar_random_slow_rsp	4.108m	28.901ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	4.860s	18.803us	1	1	100.00
		xbar_error_and_unmapped_addr	21.380s	322.254us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	17.500s	799.953us	1	1	100.00
		xbar_error_and_unmapped_addr	21.380s	322.254us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	29.050s	1.083ms	1	1	100.00
		xbar_access_same_device_slow_rsp	2.021m	13.629ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	4.500s	38.356us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.926m	3.285ms	1	1	100.00
		xbar_stress_all_with_error	5.250m	15.408ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.195m	1.209ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.761m	533.909us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.142m	15.076ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	39.657m	27.230ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.998m	15.068ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.358m	11.534ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.531m	15.632ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.978m	16.193ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	46.051m	17.895ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.545m	15.533ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.380s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.900s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	23.680s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	18.070s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.710s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.750s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.770s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	19.020s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.370s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	19.080s	10.240us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.620s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.880s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	20.830s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.120s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	19.830s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.300s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.890s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.920s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.660s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.610s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.620s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.910s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.080s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.570s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.270s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	32.422m	11.022ms	1	1	100.00
		rom_e2e_asm_init_dev	41.524m	15.649ms	1	1	100.00
		rom_e2e_asm_init_prod	41.408m	15.827ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.815m	15.635ms	1	1	100.00
		rom_e2e_asm_init_rma	41.467m	14.731ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.512m	17.474ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.710m	14.654ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.350m	16.535ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.130m	15.870ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.746m	34.703ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.746m	34.703ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.468m	2.781ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.030m	2.808ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.316m	2.855ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.965m	2.391ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.069m	6.337ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.846m	3.009ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.025m	4.563ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.161m	5.874ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.495ms	1	1	100.00
		chip_plic_all_irqs_20	5.636m	4.613ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.882m	3.305ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.562m	12.044ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.536m	3.293ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.387m	2.550ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.905m	7.533ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.479m	7.782ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.526m	7.696ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.483h	255.764ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.862m	3.449ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.609m	5.749ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.862m	3.449ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.967m	9.644ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.967m	9.644ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.109m	6.348ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.621m	4.813ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.951m	5.768ms	1	1	100.00
		chip_sw_aes_idle	1.965m	2.391ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.308m	2.794ms	1	1	100.00
		chip_sw_kmac_idle	2.506m	2.575ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.394m	4.785ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.173m	3.726ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.998m	5.649ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.064m	3.966ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.720m	11.700ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.316m	4.716ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.064m	5.217ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.112m	4.160ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.963m	4.902ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.945m	3.659ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.261m	4.646ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.226m	7.852ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.423m	5.572ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.112m	4.160ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.963m	4.902ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.162m	4.046ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.853m	6.244ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.007m	19.185ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.030m	2.808ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	14.173m	7.222ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.242m	3.091ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.707m	7.588ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.269m	3.213ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.039m	4.929ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.741m	2.949ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.197m	3.188ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.231m	4.221ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.502m	6.917ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.503m	24.783ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.885m	3.770ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.776m	3.478ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	15.254m	10.337ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.523m	2.905ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.407m	4.295ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.351m	20.452ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	37.655m	20.175ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.226m	7.852ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.743m	4.931ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.410m	3.127ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.905m	7.533ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.223m	7.282ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.289m	3.250ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.735m	5.421ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.748m	3.327ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.087h	24.665ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.968m	3.126ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.706m	5.720ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.968m	3.126ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.223m	7.282ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.704m	3.331ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	23.608m	23.125ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.453m	5.401ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.853m	6.244ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.115m	3.618ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.162m	4.046ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.060m	42.724ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	23.608m	23.125ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.257m	3.309ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.060m	42.724ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.144m	14.489ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.928m	5.135ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.228m	4.983ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.228m	4.983ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.154m	3.530ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.242m	3.091ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.308m	2.794ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.446m	2.874ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.757m	3.934ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.737m	5.735ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.658m	4.630ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.891m	4.551ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.389m	3.926ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.707m	7.588ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	17.563m	7.883ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.069m	6.337ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.439m	12.987ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.396m	2.091ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.430m	3.449ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.269m	3.213ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.451m	2.519ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.778m	5.243ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.506m	2.575ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.025m	4.563ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.052m	11.568ms	1	1	100.00
		chip_tap_straps_rma	1.266m	2.570ms	1	1	100.00
		chip_tap_straps_prod	1.561m	3.141ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.862m	3.303ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.689m	8.543ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.003m	5.084ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.060m	42.724ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.260m	3.066ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.482m	6.007ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.892m	5.785ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.430m	7.583ms	0	1	0.00
		chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.908m	8.806ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.685m	9.755ms	1	1	100.00
		chip_prim_tl_access	7.144m	14.489ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.423m	5.572ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.316m	4.716ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.064m	5.217ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.112m	4.160ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.963m	4.902ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.945m	3.659ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.261m	4.646ms	1	1	100.00
		chip_tap_straps_dev	14.052m	11.568ms	1	1	100.00
		chip_tap_straps_rma	1.266m	2.570ms	1	1	100.00
		chip_tap_straps_prod	1.561m	3.141ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.861m	5.284ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.951m	3.578ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.853m	3.755ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.636m	3.259ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.504m	3.072ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.720m	27.525ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.861m	5.284ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.114h	49.164ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.170h	48.986ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.317m	8.453ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.056h	44.463ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.720m	27.525ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.017m	2.235ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.135m	2.905ms	1	1	100.00
		rom_volatile_raw_unlock	1.035m	1.991ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.617m	17.231ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.007m	19.185ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.951m	5.768ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.951m	5.768ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.951m	5.768ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.678m	3.485ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	23.608m	23.125ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.678m	3.485ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.082m	3.821ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.699m	2.772ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	23.608m	23.125ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.678m	3.485ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.094m	9.427ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.082m	3.821ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.699m	2.772ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.136m	5.693ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.862m	3.303ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.260m	3.066ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.482m	6.007ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.892m	5.785ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.430m	7.583ms	0	1	0.00
		chip_sw_lc_ctrl_transition	6.823m	11.988ms	1	1	100.00
		chip_prim_tl_access	7.144m	14.489ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.144m	14.489ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.918m	8.338ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.689m	8.717ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.429m	24.034ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.560m	7.549ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.442m	8.138ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.139m	4.945ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	19.039m	23.194ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.095m	15.409ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.967m	9.644ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	15.655m	13.937ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.240m	3.940ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.689m	8.717ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.216m	3.189ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.873m	29.585ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.299m	6.679ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.691m	4.776ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.152m	19.820ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.239m	7.120ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.736m	11.419ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	29.302m	29.276ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.398m	3.585ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.908m	8.806ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.908m	8.806ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.736m	11.419ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.152m	19.820ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.240m	3.940ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.609m	5.749ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.441m	4.718ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.812m	4.302ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.310m	5.324ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.562m	12.044ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.255m	3.117ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	19.479m	7.782ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.350m	4.476ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.529m	5.008ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.659m	2.822ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.699m	2.772ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.812m	4.302ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.812m	4.302ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	10.161m	10.622ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.784m	13.366ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.441m	4.718ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.609m	4.964ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.985m	6.881ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.266m	2.570ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.861m	5.284ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.161m	5.874ms	1	1	100.00
		chip_plic_all_irqs_10	4.413m	3.495ms	1	1	100.00
		chip_plic_all_irqs_20	5.636m	4.613ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.847m	3.058ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.155m	3.311ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.142m	15.076ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.603m	5.415ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.377m	3.293ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.553m	2.905ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.411m	2.560ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.082m	3.821ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.039m	4.929ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.007m	8.654ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.125m	7.908ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.685m	9.755ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.725m	6.219ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.239m	7.120ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.352m	21.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.733m	3.262ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.276m	3.700ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.553m	4.087ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.352m	21.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.352m	21.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.162m	20.523ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.162m	20.523ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.032m	5.928ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.746m	34.703ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.834m	2.948ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.426m	3.084ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.630m	3.310ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.511m	4.214ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.891m	8.215ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.468h	31.101ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.609m	11.970ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.322m	3.108ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.294m	3.049ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.426m	2.614ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.593h	72.257ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.028m	6.184ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	19.794m	11.246ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.746m	3.547ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.110m	10.272ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	4.329m	4.517ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.627m	4.663ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.145m	4.680ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.356s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.287m	5.160ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.443m	3.139ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.005m	4.570ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.220m	9.812ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.369m	2.316ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.314m	5.212ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.041m	2.345ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.435m	5.425ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.205m	6.078ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.460m	4.507ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.736m	11.419ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	19.794m	11.246ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.746m	3.547ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.110m	10.272ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.681m	4.583ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.102m	5.193ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.547h	38.645ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.547h	38.645ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.844m	3.288ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.485m	4.663ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.861m	19.508ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.205m	2.442ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.401m	4.881ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	35.794m	41.310ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	3.133m	2.910ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.361m	3.109ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.512m	4.090ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.091s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.617m	2.674ms	1	1	100.00
		TOTAL			282	326	86.50

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.37911626551626406528161206051657144609947068364321193034190458657739246221149
    Line 521, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.88568238708638325501476553815491793936593518538484815429707100531876426345929
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.40948365271833649254662604103843882471978106184515177554986055901834105181910
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.9950488758991150408047072726285359499057458111467222681691806116091335665166
    Line 531, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.42037213870500320205298974444802335112517678018480151251466348790315876093892
    Line 556, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.44562392714358330322444412121231396588870356058634678646719618816350485730851
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.29115118393626250748857449100579716220684604372346573235156207062917175537878
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.11145807603906358398254439198099771006183361801140931573396525019462058088686
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.27127552256302099572144423192244729542415753148477468572863846300401892521741
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.93323378968319510413104746778511387066912169628289073706298738991549123210208
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.16784513040130552217291157815329648736820535372182552191120686871612661341134
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.28185684423347960698302552626292576899338365905147484991112167048581495651013
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.21952567973780516499948115698211072791539327585401901529921846533603045194935
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.12139351379339011073170575743926300532121319435068023359986746164720887501726
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.9906214542299507896661007306397516937889435223943899720360750284424308623972
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.149s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.86466948780842230703216356660961443573314914529643385054540394234703486470500
    Line 566, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.94319826819778186625218641308349585281804039697166339358199673517660108950208
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4952559759083722443240199103925475033839402188026822481298817079506832314729
    Line 575, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.64188837164019449227687411148825596269927218085391635960214088322282384606313
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.68845937026290481474307148768804984303617837643156561737692865298629994914196
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3292.576991 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.5596365697983226278262493253303861910068161536334555209028518988707952723882
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7583.456552 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7583.456552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.103341823937438757529983183356002024439016767571433354834574428769432472303981
    Line 436, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 41310.012744 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 41310.012744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79986) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.3615222408771960953074022946760097846439721713120441552523348217132682120826
Line 431, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4302.348016 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@79986) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4302.348016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.31227865767277289611071244439789479182743156659980152970293392061925755402026
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34703.371537 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34703.371537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.114236037262856089906113901787350167498074833170403754335806017874938711633852
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3008.721912 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3008.721912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.50232690636226410533324728340779189104040508165816836745091547135973889797123
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2549.607295 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2549.607295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.79902472852329783266248501897083957077324553441103219596680608519226905358706
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.76549436223338004179516038058889302631280432421479555782303395276950934354167
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2873.661914 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2873.661914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38208) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1052430832314985452026536677530211407475358845209889758687138531379081323050
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2859.794814 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38208) { a_addr: 'h10648  a_data: 'h29648f39  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1a28a  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2859.794814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.21778049016019515391685112643919353995270316763561315678366681570541541126778
    Line 219, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 5284.150263 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1079c read out mismatch
  UVM_INFO @ 5284.150263 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.50305666545768208902452303149254035582584586443873505064447285280627577992101
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2614.268096 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2614.268096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.75570490298441659775572559507591478912264583024344112571595999434024976077307
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2913.675000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2913.675000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.13979025821730793452210058983705108583744268675871902987239984463856205598246
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2931.492000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2931.492000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.14645302116058110293715999690142974579940095138673697527770073047269141649940
    Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 14726.962533 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 14726.962533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.64740481665812015107744398746304142903597712258615880696113381526951348868028
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.68099017471093460221489757675370649409676823723336306074845292822152292036166
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.82528363917597891772704126468254025792866582282947896959027590644930300070620
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 3546.524530 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3546.524530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32190) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.18841283254157535807520412265125691433358832019448391722647929225286145711221
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2484.318748 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32190) { a_addr: 'h10728  a_data: 'hec80ad6c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h4  a_user: 'h195e9  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2484.318748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---