ADC_CTRL Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.140s	5.766ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.000s	727.088us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.070s	398.995us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.380s	2.102ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.220s	982.356us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.700s	510.401us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.070s	398.995us	1	1	100.00
		adc_ctrl_csr_aliasing	2.220s	982.356us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	30.320s	163.395ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.098m	327.201ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	6.511m	325.139ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.294m	170.580ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	7.310m	563.519ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.391m	192.070ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.589m	329.179ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.751m	408.123ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.300s	4.304ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	4.740s	22.541ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.170m	108.512ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.566m	277.321ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.270s	490.718us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.060s	467.003us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.520s	451.495us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.520s	451.495us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.000s	727.088us	1	1	100.00
		adc_ctrl_csr_rw	1.070s	398.995us	1	1	100.00
		adc_ctrl_csr_aliasing	2.220s	982.356us	1	1	100.00
		adc_ctrl_same_csr_outstanding	12.210s	4.022ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.000s	727.088us	1	1	100.00
		adc_ctrl_csr_rw	1.070s	398.995us	1	1	100.00
		adc_ctrl_csr_aliasing	2.220s	982.356us	1	1	100.00
		adc_ctrl_same_csr_outstanding	12.210s	4.022ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.880s	7.622ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.530s	4.637ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.530s	4.637ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.750s	9.652ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00