AES/MASKED Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: `0fc384d`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	73.288us	1	1	100.00
V1	smoke	aes_smoke	3.000s	79.794us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	142.215us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	76.293us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	3.000s	197.667us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	324.685us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	75.451us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	76.293us	1	1	100.00
		aes_csr_aliasing	3.000s	324.685us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	79.794us	1	1	100.00
		aes_config_error	3.000s	434.771us	1	1	100.00
		aes_stress	4.000s	377.084us	1	1	100.00
V2	key_length	aes_smoke	3.000s	79.794us	1	1	100.00
		aes_config_error	3.000s	434.771us	1	1	100.00
		aes_stress	4.000s	377.084us	1	1	100.00
V2	back2back	aes_stress	4.000s	377.084us	1	1	100.00
		aes_b2b	11.000s	445.418us	1	1	100.00
V2	backpressure	aes_stress	4.000s	377.084us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	79.794us	1	1	100.00
		aes_config_error	3.000s	434.771us	1	1	100.00
		aes_stress	4.000s	377.084us	1	1	100.00
		aes_alert_reset	42.000s	6.287ms	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	126.893us	1	1	100.00
		aes_config_error	3.000s	434.771us	1	1	100.00
		aes_alert_reset	42.000s	6.287ms	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	145.182us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	593.920us	1	1	100.00
V2	reset_recovery	aes_alert_reset	42.000s	6.287ms	1	1	100.00
V2	stress	aes_stress	4.000s	377.084us	1	1	100.00
V2	sideload	aes_stress	4.000s	377.084us	1	1	100.00
		aes_sideload	3.000s	355.892us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	231.785us	1	1	100.00
V2	stress_all	aes_stress_all	34.000s	2.348ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	56.424us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	69.178us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	69.178us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	142.215us	1	1	100.00
		aes_csr_rw	1.000s	76.293us	1	1	100.00
		aes_csr_aliasing	3.000s	324.685us	1	1	100.00
		aes_same_csr_outstanding	2.000s	66.310us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	142.215us	1	1	100.00
		aes_csr_rw	1.000s	76.293us	1	1	100.00
		aes_csr_aliasing	3.000s	324.685us	1	1	100.00
		aes_same_csr_outstanding	2.000s	66.310us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	4.000s	105.889us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	322.641us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	464.104us	1	1	100.00
		aes_tl_intg_err	3.000s	455.074us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	455.074us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	42.000s	6.287ms	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	79.794us	1	1	100.00
		aes_stress	4.000s	377.084us	1	1	100.00
		aes_alert_reset	42.000s	6.287ms	1	1	100.00
		aes_core_fi	1.000s	5.110us	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	116.680us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	101.278us	1	1	100.00
		aes_stress	4.000s	377.084us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	377.084us	1	1	100.00
		aes_sideload	3.000s	355.892us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	101.278us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	101.278us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	101.278us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	101.278us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	101.278us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	377.084us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	377.084us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	136.922us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	136.922us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	68.727us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	136.922us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	42.000s	6.287ms	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_ctr_fi	2.000s	64.565us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	136.922us	1	1	100.00
		aes_control_fi	2.000s	87.911us	1	1	100.00
		aes_cipher_fi	2.000s	68.727us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	832.163us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

0.aes_core_fi.18126465444116289121007544785386153007234108197321990128027229664337306990440
Line 131, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 5110147 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 5098242 PS)
  UVM_ERROR @   5110147 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @   5110147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.94065322671175318507066841792940739123315711312964430085325232904155739783434
    Line 164, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 832163409 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 832163409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```