EDN Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.980s	32.232us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.840s	14.227us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.870s	42.935us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.490s	65.380us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.130s	33.965us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.880s	45.656us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.870s	42.935us	1	1	100.00
		edn_csr_aliasing	1.130s	33.965us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.210s	97.428us	1	1	100.00
V2	csrng_commands	edn_genbits	1.210s	97.428us	1	1	100.00
V2	genbits	edn_genbits	1.210s	97.428us	1	1	100.00
V2	interrupts	edn_intr	1.000s	48.287us	1	1	100.00
V2	alerts	edn_alert	1.340s	75.423us	1	1	100.00
V2	errs	edn_err	0.910s	114.576us	1	1	100.00
V2	disable	edn_disable	0.830s	35.914us	1	1	100.00
		edn_disable_auto_req_mode	1.020s	86.583us	1	1	100.00
V2	stress_all	edn_stress_all	3.390s	416.221us	1	1	100.00
V2	intr_test	edn_intr_test	0.860s	18.812us	1	1	100.00
V2	alert_test	edn_alert_test	0.850s	27.290us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.770s	87.981us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.770s	87.981us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.840s	14.227us	1	1	100.00
		edn_csr_rw	0.870s	42.935us	1	1	100.00
		edn_csr_aliasing	1.130s	33.965us	1	1	100.00
		edn_same_csr_outstanding	1.070s	40.342us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.840s	14.227us	1	1	100.00
		edn_csr_rw	0.870s	42.935us	1	1	100.00
		edn_csr_aliasing	1.130s	33.965us	1	1	100.00
		edn_same_csr_outstanding	1.070s	40.342us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.150s	402.702us	1	1	100.00
		edn_tl_intg_err	1.690s	139.548us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.920s	50.517us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.340s	75.423us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.150s	402.702us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.150s	402.702us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.150s	402.702us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.150s	402.702us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.340s	75.423us	1	1	100.00
		edn_sec_cm	3.150s	402.702us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.340s	75.423us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.690s	139.548us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.202m	9.055ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00