| V1 |
smoke |
hmac_smoke |
11.580s |
3.794ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
0.970s |
29.514us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
0.780s |
28.197us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
4.230s |
915.746us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
6.120s |
1.034ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
0.980s |
53.682us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
0.780s |
28.197us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.120s |
1.034ms |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
12.650s |
1.189ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
37.950s |
2.028ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
3.126m |
46.044ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.789m |
69.727ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
19.920s |
4.513ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.190s |
231.468us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
6.900s |
236.363us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.750s |
662.551us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
28.100s |
769.946us |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
2.481m |
5.283ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
48.470s |
3.907ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.308m |
38.629ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
11.580s |
3.794ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
12.650s |
1.189ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.950s |
2.028ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
2.481m |
5.283ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
28.100s |
769.946us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
10.930s |
642.556us |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
11.580s |
3.794ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
12.650s |
1.189ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.950s |
2.028ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
2.481m |
5.283ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.308m |
38.629ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
3.126m |
46.044ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.789m |
69.727ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
19.920s |
4.513ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.190s |
231.468us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
6.900s |
236.363us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.750s |
662.551us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
11.580s |
3.794ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
12.650s |
1.189ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
37.950s |
2.028ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
2.481m |
5.283ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
28.100s |
769.946us |
1 |
1 |
100.00 |
|
|
hmac_error |
48.470s |
3.907ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.308m |
38.629ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
3.126m |
46.044ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
5.789m |
69.727ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
19.920s |
4.513ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.190s |
231.468us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
6.900s |
236.363us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.750s |
662.551us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
10.930s |
642.556us |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
10.930s |
642.556us |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
0.770s |
11.182us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
0.760s |
21.522us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
2.700s |
484.605us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
2.700s |
484.605us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
0.970s |
29.514us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
0.780s |
28.197us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.120s |
1.034ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.480s |
92.560us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
0.970s |
29.514us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
0.780s |
28.197us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.120s |
1.034ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.480s |
92.560us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.110s |
118.145us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
3.290s |
502.521us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
3.290s |
502.521us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
11.580s |
3.794ms |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
4.520s |
434.912us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
2.617m |
16.310ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
3.320s |
54.939us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |