I2C Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	50.720s	1.650ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.310s	4.325ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	53.981us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.840s	70.324us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.800s	1.051ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.100s	71.937us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.830s	47.967us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.840s	70.324us	1	1	100.00
		i2c_csr_aliasing	1.100s	71.937us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.720s	166.381us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	9.283m	17.588ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	23.648m	51.296ms	1	1	100.00
V2	host_override	i2c_host_override	0.760s	26.215us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.578m	16.184ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	56.950s	10.978ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.040s	477.393us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.910s	1.462ms	1	1	100.00
		i2c_host_fifo_reset_rx	2.970s	936.005us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	57.380s	3.712ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.920s	2.825ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.500s	154.862us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.040s	1.135ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	47.830s	25.601ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.800s	6.009ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	3.340s	384.468us	1	1	100.00
		i2c_target_intr_smoke	4.580s	2.258ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.980s	199.795us	1	1	100.00
		i2c_target_fifo_reset_tx	1.270s	1.074ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.339m	41.402ms	1	1	100.00
		i2c_target_stress_rd	3.340s	384.468us	1	1	100.00
		i2c_target_intr_stress_wr	2.898m	19.776ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.920s	1.484ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.840s	1.120ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.600s	2.059ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.830s	10.057ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.000s	558.452us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.210s	1.122ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	23.648m	51.296ms	1	1	100.00
		i2c_host_perf_precise	1.630s	277.037us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.920s	2.825ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.240s	269.867us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.190s	1.014ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.150s	1.002ms	1	1	100.00
		i2c_target_nack_txstretch	1.970s	273.934us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.900s	1.062ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.860s	743.174us	1	1	100.00
V2	alert_test	i2c_alert_test	0.620s	48.421us	1	1	100.00
V2	intr_test	i2c_intr_test	0.690s	46.484us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.600s	64.704us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.600s	64.704us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	53.981us	1	1	100.00
		i2c_csr_rw	0.840s	70.324us	1	1	100.00
		i2c_csr_aliasing	1.100s	71.937us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	268.699us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	53.981us	1	1	100.00
		i2c_csr_rw	0.840s	70.324us	1	1	100.00
		i2c_csr_aliasing	1.100s	71.937us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	268.699us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.630s	171.250us	1	1	100.00
		i2c_sec_cm	0.950s	64.980us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.630s	171.250us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.080s	1.326ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.210s	324.242us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.100s	343.110us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.83904979295411500053520169071558734005378849992350702867779270050277436703846
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 166380589 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 166380589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.34798109801541751210321233302123242245503988170421913705674587594924938543650
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 17588020256 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 17588020256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.64864441141075354948919849565033924605279460626247266645993894174628836773948
      Line 98, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 343109639 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 343109639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.100740019802786370255508981226666692265463844967503154001775327847518972591407
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1135230408 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1135230408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.39526502067548494250591784888178467192354736559493214439510775777723736827258
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 324242133 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 324242133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.59688518270872141861535064080398628471272309651867883657276662890449985290554
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10057337730 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10057337730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.12579042970212603354609130971434616855289123099273446769818491630664964158975
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1325606241 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1325606241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.30947568124142154702308295987504641632184132532616511863189132231982130081285
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 154861799 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------