KEYMGR Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.940s 58.025us 1 1 100.00
V1 random keymgr_random 13.780s 2.701ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.000s 63.023us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.280s 55.936us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 21.600s 2.338ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 4.790s 251.944us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.270s 162.075us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.280s 55.936us 1 1 100.00
keymgr_csr_aliasing 4.790s 251.944us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 8.980s 913.141us 1 1 100.00
V2 sideload keymgr_sideload 10.170s 1.202ms 1 1 100.00
keymgr_sideload_kmac 2.880s 133.201us 1 1 100.00
keymgr_sideload_aes 1.870s 433.462us 1 1 100.00
keymgr_sideload_otbn 14.120s 713.199us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 4.540s 348.300us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.570s 99.613us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.800s 235.402us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 6.320s 785.224us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.560s 91.630us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.260s 231.820us 1 1 100.00
V2 stress_all keymgr_stress_all 11.920s 1.710ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.880s 21.170us 1 1 100.00
V2 alert_test keymgr_alert_test 0.830s 19.609us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 3.120s 223.593us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 3.120s 223.593us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.000s 63.023us 1 1 100.00
keymgr_csr_rw 1.280s 55.936us 1 1 100.00
keymgr_csr_aliasing 4.790s 251.944us 1 1 100.00
keymgr_same_csr_outstanding 1.920s 352.826us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.000s 63.023us 1 1 100.00
keymgr_csr_rw 1.280s 55.936us 1 1 100.00
keymgr_csr_aliasing 4.790s 251.944us 1 1 100.00
keymgr_same_csr_outstanding 1.920s 352.826us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
keymgr_tl_intg_err 2.010s 326.323us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.510s 251.652us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.510s 251.652us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.510s 251.652us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.510s 251.652us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 4.390s 231.832us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.010s 326.323us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.510s 251.652us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 8.980s 913.141us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 13.780s 2.701ms 1 1 100.00
keymgr_csr_rw 1.280s 55.936us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 13.780s 2.701ms 1 1 100.00
keymgr_csr_rw 1.280s 55.936us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 13.780s 2.701ms 1 1 100.00
keymgr_csr_rw 1.280s 55.936us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.570s 99.613us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.560s 91.630us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.560s 91.630us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 13.780s 2.701ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 3.040s 279.704us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 4.750s 283.032us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.570s 99.613us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 4.750s 283.032us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 4.750s 283.032us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 4.750s 283.032us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 5.850s 4.495ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 4.750s 283.032us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 6.740s 145.693us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00