KMAC/MASKED Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	53.510s	4.178ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.950s	17.086us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.860s	56.929us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.440s	984.641us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.730s	2.752ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.930s	34.251us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.860s	56.929us	1	1	100.00
		kmac_csr_aliasing	3.730s	2.752ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.750s	20.490us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.990s	17.767us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.994m	125.394ms	1	1	100.00
V2	burst_write	kmac_burst_write	15.476m	26.281ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.754m	106.680ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.900s	7.512ms	1	1	100.00
		kmac_test_vectors_sha3_384	25.040s	6.248ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.510s	737.452us	1	1	100.00
		kmac_test_vectors_shake_128	2.296m	66.908ms	1	1	100.00
		kmac_test_vectors_shake_256	5.240m	20.887ms	1	1	100.00
		kmac_test_vectors_kmac	2.620s	328.624us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.830s	440.423us	1	1	100.00
V2	sideload	kmac_sideload	3.344m	38.559ms	1	1	100.00
V2	app	kmac_app	1.334m	3.988ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.292m	10.251ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.782m	6.111ms	1	1	100.00
V2	error	kmac_error	17.910s	397.835us	1	1	100.00
V2	key_error	kmac_key_error	13.450s	2.130ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.290s	828.989us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	26.800s	1.444ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.070s	72.240us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.140s	1.655ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	17.820s	3.625ms	1	1	100.00
V2	stress_all	kmac_stress_all	3.260m	5.925ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.750s	51.851us	1	1	100.00
V2	alert_test	kmac_alert_test	1.010s	48.792us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.670s	67.276us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.670s	67.276us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.950s	17.086us	1	1	100.00
		kmac_csr_rw	0.860s	56.929us	1	1	100.00
		kmac_csr_aliasing	3.730s	2.752ms	1	1	100.00
		kmac_same_csr_outstanding	2.200s	352.814us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.950s	17.086us	1	1	100.00
		kmac_csr_rw	0.860s	56.929us	1	1	100.00
		kmac_csr_aliasing	3.730s	2.752ms	1	1	100.00
		kmac_same_csr_outstanding	2.200s	352.814us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	48.632us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	48.632us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	48.632us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	48.632us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.060s	47.554us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	27.110s	8.379ms	1	1	100.00
		kmac_tl_intg_err	3.300s	664.817us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.300s	664.817us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	17.820s	3.625ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	53.510s	4.178ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.344m	38.559ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	48.632us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.110s	8.379ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.110s	8.379ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.110s	8.379ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	53.510s	4.178ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	17.820s	3.625ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.110s	8.379ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	53.350s	2.556ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	53.510s	4.178ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	53.920s	1.315ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.3699551850562895458355541706463733211265685658674011617171505661164827282525
      Line 226, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1314974357 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1314974357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---