OTBN Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 13.000s 62.075us 0 1 0.00
V1 single_binary otbn_single 7.000s 85.292us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 3.000s 42.803us 1 1 100.00
V1 csr_rw otbn_csr_rw 3.000s 13.873us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 117.950us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 3.000s 20.429us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 65.192us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 3.000s 13.873us 1 1 100.00
otbn_csr_aliasing 3.000s 20.429us 1 1 100.00
V1 mem_walk otbn_mem_walk 26.000s 11.978ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 190.612us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 30.000s 110.082us 0 1 0.00
V2 multi_error otbn_multi_err 40.000s 706.013us 0 1 0.00
V2 back_to_back otbn_multi 29.000s 110.212us 0 1 0.00
V2 stress_all otbn_stress_all 24.000s 844.124us 0 1 0.00
V2 lc_escalation otbn_escalate 5.000s 23.893us 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 38.724us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 9.000s 57.894us 0 1 0.00
V2 alert_test otbn_alert_test 3.000s 13.286us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 39.543us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 4.000s 228.750us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 4.000s 228.750us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 3.000s 42.803us 1 1 100.00
otbn_csr_rw 3.000s 13.873us 1 1 100.00
otbn_csr_aliasing 3.000s 20.429us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.384us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 3.000s 42.803us 1 1 100.00
otbn_csr_rw 3.000s 13.873us 1 1 100.00
otbn_csr_aliasing 3.000s 20.429us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.384us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 7.000s 20.226us 0 1 0.00
otbn_dmem_err 8.000s 38.180us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 259.811us 0 1 0.00
otbn_controller_ispr_rdata_err 7.000s 124.475us 0 1 0.00
otbn_mac_bignum_acc_err 9.000s 59.519us 0 1 0.00
otbn_urnd_err 5.000s 10.377us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 5.000s 29.795us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 4.000s 21.806us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 5.000s 26.691us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 11.000s 196.292us 0 1 0.00
otbn_tl_intg_err 1.000m 432.484us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 30.000s 246.614us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S prim_count_check otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 13.000s 62.075us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 8.000s 38.180us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 20.226us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.000m 432.484us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 5.000s 23.893us 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 20.226us 0 1 0.00
otbn_dmem_err 8.000s 38.180us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 38.724us 1 1 100.00
otbn_illegal_mem_acc 5.000s 29.795us 1 1 100.00
otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 20.226us 0 1 0.00
otbn_dmem_err 8.000s 38.180us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 38.724us 1 1 100.00
otbn_illegal_mem_acc 5.000s 29.795us 1 1 100.00
otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 5.000s 23.893us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 20.226us 0 1 0.00
otbn_dmem_err 8.000s 38.180us 0 1 0.00
otbn_zero_state_err_urnd 6.000s 38.724us 1 1 100.00
otbn_illegal_mem_acc 5.000s 29.795us 1 1 100.00
otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 4.000s 160.901us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 6.000s 19.803us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 28.000s 520.453us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 28.000s 520.453us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 5.000s 77.257us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 8.000s 158.243us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 102.154us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 8.000s 102.154us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 5.000s 135.246us 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 29.000s 110.212us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 5.000s 149.379us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 7.000s 85.292us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 11.000s 196.292us 0 1 0.00
V2S TOTAL 6 20 30.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 5.233m 1.663ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 41 43.90

Failure Buckets