PATTGEN Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	61.021us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	34.861us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	57.006us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	239.019us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	69.403us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	26.641us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	57.006us	1	1	100.00
		pattgen_csr_aliasing	2.000s	69.403us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	1.117m	2.806ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	10.000s	2.694ms	1	1	100.00
V2	error	pattgen_error	2.000s	41.118us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.167m	23.712ms	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	49.639us	1	1	100.00
V2	intr_test	pattgen_intr_test	2.000s	44.470us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	3.000s	127.215us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	3.000s	127.215us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	34.861us	1	1	100.00
		pattgen_csr_rw	1.000s	57.006us	1	1	100.00
		pattgen_csr_aliasing	2.000s	69.403us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	67.703us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	34.861us	1	1	100.00
		pattgen_csr_rw	1.000s	57.006us	1	1	100.00
		pattgen_csr_aliasing	2.000s	69.403us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	67.703us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	1.000s	202.519us	1	1	100.00
		pattgen_sec_cm	1.000s	68.443us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	202.519us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	23.000s	40.037ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	44.000s	10.158ms	0	1	0.00
		TOTAL			15	18	83.33

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.5258828358192142201390280793908384379698534243995637534624489733054014927269
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10158048007 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xfd7e0a50, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
        UVM_INFO @ 10158048007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.94720293475989354057246743429541469451441518202786265159133823135684176287422
      Line 199, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17777298796 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 17777356232 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 17777356232 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 17778522901 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.97682587761439420488187437180897162515624046799834590819114587929904865870295
      Line 132, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @ 23711819715 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10147