ROM_CTRL/32KB Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.230s 545.448us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.140s 599.736us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 3.420s 371.095us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.240s 174.728us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.030s 468.500us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.380s 173.577us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 3.420s 371.095us 1 1 100.00
rom_ctrl_csr_aliasing 4.030s 468.500us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.320s 538.056us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.450s 534.324us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.540s 507.251us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 21.890s 13.235ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.530s 225.198us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.700s 127.146us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.720s 535.946us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.720s 535.946us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.140s 599.736us 1 1 100.00
rom_ctrl_csr_rw 3.420s 371.095us 1 1 100.00
rom_ctrl_csr_aliasing 4.030s 468.500us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.250s 175.167us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.140s 599.736us 1 1 100.00
rom_ctrl_csr_rw 3.420s 371.095us 1 1 100.00
rom_ctrl_csr_aliasing 4.030s 468.500us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.250s 175.167us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.280s 593.127us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
rom_ctrl_tl_intg_err 27.110s 662.463us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.230s 545.448us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.230s 545.448us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.230s 545.448us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 27.110s 662.463us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.530s 225.198us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 57.410s 3.628ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.280s 593.127us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.349m 1.937ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.982m 12.722ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00