RV_TIMER Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.700s	42.520us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.660s	12.411us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.660s	12.342us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.020s	67.879us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.850s	273.840us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.980s	41.480us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.660s	12.342us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	273.840us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.660s	120.728us	0	1	0.00
V2	disabled	rv_timer_disabled	1.460s	727.607us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.277m	116.215ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.277m	116.215ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.430s	2.933ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.650s	46.791us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.650s	19.354us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.050s	258.013us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.050s	258.013us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.660s	12.411us	1	1	100.00
		rv_timer_csr_rw	0.660s	12.342us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	273.840us	1	1	100.00
		rv_timer_same_csr_outstanding	0.790s	68.005us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.660s	12.411us	1	1	100.00
		rv_timer_csr_rw	0.660s	12.342us	1	1	100.00
		rv_timer_csr_aliasing	0.850s	273.840us	1	1	100.00
		rv_timer_same_csr_outstanding	0.790s	68.005us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.890s	380.739us	1	1	100.00
		rv_timer_tl_intg_err	1.630s	130.895us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.630s	130.895us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.770s	65.277us	0	1	0.00
V3	max_value	rv_timer_max	0.770s	48.340us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.710s	2.902ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			15	19	78.95

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.63073423694152950532080603980172462800484294441316598648663135557648776450723
      Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  65277188 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x843e4d04) == 0x1
        UVM_INFO @  65277188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.84600279385375038935400745024775338275980668724988086524176400899753207307549
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 120727617 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7a0a3d04) == 0x1
        UVM_INFO @ 120727617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.76853858294409619399192933099463475987339227063015103680696459360710344035315
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  48340400 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  48340400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.48679167633907111982573350832715874521549522019920163515725095825479635113624
      Line 227, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2901871588 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 2901871588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---