SPI_DEVICE/2P Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	57.630s	23.040ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.220s	30.085us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.270s	36.118us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.390s	724.141us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.770s	435.319us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.850s	161.521us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.270s	36.118us	1	1	100.00
		spi_device_csr_aliasing	5.770s	435.319us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.940s	27.735us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.550s	27.788us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	66.933us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.030s	86.000us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.690s	17.418us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.840s	39.768us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.840s	39.768us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.150s	1.126ms	1	1	100.00
		spi_device_tpm_sts_read	0.670s	26.124us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.110s	1.085ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.250s	749.446us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.210s	983.162us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.210s	983.162us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.650s	207.198us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.650s	207.198us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.650s	207.198us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.650s	207.198us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.650s	207.198us	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	10.410s	4.888ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	36.850s	13.241ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	36.850s	13.241ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	36.850s	13.241ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.000s	2.017ms	1	1	100.00
		spi_device_read_buffer_direct	6.760s	6.614ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	36.850s	13.241ms	1	1	100.00
		spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	quad_spi	spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	dual_spi	spi_device_flash_all	0.820s	173.650us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.040s	697.591us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.040s	697.591us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	57.630s	23.040ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.085m	97.931ms	1	1	100.00
V2	stress_all	spi_device_stress_all	11.294m	448.449ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.830s	43.294us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.930s	11.627us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.370s	365.334us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.370s	365.334us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.220s	30.085us	1	1	100.00
		spi_device_csr_rw	1.270s	36.118us	1	1	100.00
		spi_device_csr_aliasing	5.770s	435.319us	1	1	100.00
		spi_device_same_csr_outstanding	1.560s	67.627us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.220s	30.085us	1	1	100.00
		spi_device_csr_rw	1.270s	36.118us	1	1	100.00
		spi_device_csr_aliasing	5.770s	435.319us	1	1	100.00
		spi_device_same_csr_outstanding	1.560s	67.627us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.110s	45.680us	1	1	100.00
		spi_device_tl_intg_err	15.760s	825.674us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.760s	825.674us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	45.540s	28.843ms	1	1	100.00
		TOTAL			33	33	100.00