SPI_HOST Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	25.000s	1.972ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	37.988us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	60.107us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	1.000s	68.427us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	69.191us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	24.592us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	60.107us	1	1	100.00
		spi_host_csr_aliasing	1.000s	69.191us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	21.543us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	32.558us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	19.141us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	87.590us	1	1	100.00
		spi_host_error_cmd	1.000s	16.759us	1	1	100.00
		spi_host_event	11.000s	1.719ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	438.180us	1	1	100.00
V2	speed	spi_host_speed	4.000s	438.180us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	438.180us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	30.000s	1.356ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	92.181us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	438.180us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	438.180us	1	1	100.00
V2	duplex	spi_host_smoke	25.000s	1.972ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	25.000s	1.972ms	1	1	100.00
V2	stress_all	spi_host_stress_all	15.000s	2.100ms	1	1	100.00
V2	spien	spi_host_spien	14.000s	3.346ms	1	1	100.00
V2	stall	spi_host_status_stall	29.000s	950.970us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	1.258ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	87.590us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	17.052us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	16.477us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	31.997us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	31.997us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	37.988us	1	1	100.00
		spi_host_csr_rw	1.000s	60.107us	1	1	100.00
		spi_host_csr_aliasing	1.000s	69.191us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	32.311us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	37.988us	1	1	100.00
		spi_host_csr_rw	1.000s	60.107us	1	1	100.00
		spi_host_csr_aliasing	1.000s	69.191us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	32.311us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	358.994us	1	1	100.00
		spi_host_sec_cm	1.000s	350.778us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	358.994us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.317m	25.420ms	1	1	100.00
		TOTAL			26	26	100.00