SRAM_CTRL/MAIN Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.300s	5.768ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.880s	23.224us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.770s	21.804us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.110s	51.065us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.960s	21.089us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.210s	1.305ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.770s	21.804us	1	1	100.00
		sram_ctrl_csr_aliasing	0.960s	21.089us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.936m	7.000ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.763m	2.532ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.687m	6.361ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.850m	4.598ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.557m	152.423ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.332m	36.382ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.610s	10.665ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.610m	91.142ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.490s	3.633ms	1	1	100.00
		sram_ctrl_partial_access_b2b	7.276m	101.676ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	47.030s	2.941ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	54.670s	789.102us	1	1	100.00
		sram_ctrl_throughput_w_readback	14.230s	1.533ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.386m	3.713ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.480s	1.357ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	28.886m	290.719ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.820s	38.424us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.350s	124.545us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.350s	124.545us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.880s	23.224us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	21.804us	1	1	100.00
		sram_ctrl_csr_aliasing	0.960s	21.089us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	116.648us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.880s	23.224us	1	1	100.00
		sram_ctrl_csr_rw	0.770s	21.804us	1	1	100.00
		sram_ctrl_csr_aliasing	0.960s	21.089us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	116.648us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	22.680s	3.698ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
		sram_ctrl_tl_intg_err	2.090s	196.113us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.090s	196.113us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.386m	3.713ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.386m	3.713ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.770s	21.804us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.610m	91.142ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.610m	91.142ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.610m	91.142ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.610s	10.665ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.770s	689.271us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	22.680s	3.698ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.790s	2.777ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.300s	5.768ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.300s	5.768ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.610m	91.142ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.610s	10.665ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.300s	5.768ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.850s	16.806us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.580s	471.140us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.18879007468840389860222934624632679562301937690334476291704298803438788994404
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 689271122 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 689271122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.34293133146331343888999646690534745378837735874949827109417053523210535723226
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  16806013 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  16806013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---