SRAM_CTRL/RET Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.160s	244.295us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.650s	117.728us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.630s	34.309us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.050s	88.918us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.660s	27.594us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.820s	42.149us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.630s	34.309us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	27.594us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.260s	336.965us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.680s	517.648us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.872m	3.403ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.710m	6.348ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.330s	1.570ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.046m	29.771ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.270s	607.371us	1	1	100.00
V2	executable	sram_ctrl_executable	4.515m	10.151ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.700s	4.580ms	1	1	100.00
		sram_ctrl_partial_access_b2b	7.670m	93.525ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	8.000s	282.232us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.700s	107.092us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.480s	356.437us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.775m	8.728ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.750s	78.960us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	26.228m	26.172ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	16.703us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.480s	160.416us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.480s	160.416us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.650s	117.728us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	34.309us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	27.594us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	18.178us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.650s	117.728us	1	1	100.00
		sram_ctrl_csr_rw	0.630s	34.309us	1	1	100.00
		sram_ctrl_csr_aliasing	0.660s	27.594us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.700s	18.178us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.580s	1.622ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
		sram_ctrl_tl_intg_err	1.610s	189.464us	0	1	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.610s	189.464us	0	1	0.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.775m	8.728ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.775m	8.728ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.630s	34.309us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.515m	10.151ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.515m	10.151ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.515m	10.151ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.270s	607.371us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.890s	107.477us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.580s	1.622ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.860s	49.596us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.160s	244.295us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.160s	244.295us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.515m	10.151ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.270s	607.371us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.160s	244.295us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	13.112us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.530s	356.700us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.41923021806264623379502071563311409225091289780904772983740409229325020680218
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 107476769 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 107476769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.21091929072498373488093643050947846498285905464875751873488023864500852071661
      Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  13111702 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  13111702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 0.sram_ctrl_tl_intg_err.1611514399581218683484465684389429024918085541466339432795816567037097101959
      Line 324, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 189463612 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 189463612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---