SYSRST_CTRL Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.650s	2.110ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.920s	2.461ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.020s	2.425ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.220s	2.588ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	9.430s	6.046ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.420s	2.033ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.323m	39.712ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.430s	3.227ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.710s	2.508ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.420s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.430s	3.227ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.629m	93.941ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	22.210s	25.629ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.310s	3.377ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	1.840s	2.625ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	5.490s	2.512ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.520s	2.034ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.660s	4.036ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.110s	2.622ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	3.730s	7.069ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	16.890s	34.870ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.720s	8.947ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	1.120s	2.062ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.660s	2.047ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	6.210s	2.108ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	6.210s	2.108ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	9.430s	6.046ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.420s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.430s	3.227ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.610s	8.282ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	9.430s	6.046ms	1	1	100.00
		sysrst_ctrl_csr_rw	4.420s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.430s	3.227ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	5.610s	8.282ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	21.650s	42.111ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	12.450s	22.275ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	12.450s	22.275ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.390s	3.132ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-* has 1 failures:
  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_with_pre_cond.83570234349839882985406781962329522274050674713702555331276975074537882230429
      Line 394, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 25628569335 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-4
        UVM_ERROR @ 25628569335 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-4
        UVM_INFO @ 25628569335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---