UART Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.300s	885.473us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.670s	14.575us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.690s	32.775us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.740s	116.392us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.650s	64.625us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.640s	83.339us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	32.775us	1	1	100.00
		uart_csr_aliasing	0.650s	64.625us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	32.850s	31.474ms	1	1	100.00
V2	parity	uart_smoke	1.300s	885.473us	1	1	100.00
		uart_tx_rx	32.850s	31.474ms	1	1	100.00
V2	parity_error	uart_intr	4.150s	8.369ms	1	1	100.00
		uart_rx_parity_err	46.320s	45.717ms	1	1	100.00
V2	watermark	uart_tx_rx	32.850s	31.474ms	1	1	100.00
		uart_intr	4.150s	8.369ms	1	1	100.00
V2	fifo_full	uart_fifo_full	10.890s	38.854ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.070s	41.839ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	32.780s	113.965ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.150s	8.369ms	1	1	100.00
V2	rx_break_err	uart_intr	4.150s	8.369ms	1	1	100.00
V2	rx_timeout	uart_intr	4.150s	8.369ms	1	1	100.00
V2	perf	uart_perf	15.675m	24.169ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.020s	428.703us	1	1	100.00
V2	line_loopback	uart_loopback	1.020s	428.703us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	0.870s	1.163ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.100s	2.150ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.360s	1.918ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	12.660s	3.913ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.213m	120.251ms	1	1	100.00
V2	stress_all	uart_stress_all	2.877m	163.175ms	1	1	100.00
V2	alert_test	uart_alert_test	0.720s	15.630us	1	1	100.00
V2	intr_test	uart_intr_test	0.610s	31.780us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.130s	33.175us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.130s	33.175us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.670s	14.575us	1	1	100.00
		uart_csr_rw	0.690s	32.775us	1	1	100.00
		uart_csr_aliasing	0.650s	64.625us	1	1	100.00
		uart_same_csr_outstanding	0.720s	17.303us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.670s	14.575us	1	1	100.00
		uart_csr_rw	0.690s	32.775us	1	1	100.00
		uart_csr_aliasing	0.650s	64.625us	1	1	100.00
		uart_same_csr_outstanding	0.720s	17.303us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.300s	60.926us	1	1	100.00
		uart_tl_intg_err	1.110s	132.326us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.110s	132.326us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	49.670s	14.621ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.40409684124164095261463213109566866074107092062085278777346523138976306837601
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 1125003038 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1125885398 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1126650110 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1127414822 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1128179534 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0