CHIP Simulation Results

Tuesday October 14 2025 19:33:36 UTC

GitHub Revision: `0fc384d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.785m	2.517ms	1	1	100.00
		chip_sw_example_rom	1.002m	2.171ms	1	1	100.00
		chip_sw_example_manufacturer	1.647m	2.357ms	1	1	100.00
		chip_sw_example_concurrency	2.818m	2.744ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.725m	5.206ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.354m	5.698ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.204h	59.455ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.158h	37.338ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	47.150s	2.380ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.158h	37.338ms	1	1	100.00
		chip_csr_rw	5.354m	5.698ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.210s	226.726us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.713m	3.947ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.713m	3.947ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.713m	3.947ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.105m	4.242ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.105m	4.242ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.183m	4.452ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.082m	4.108ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.416m	4.225ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.918m	8.234ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	7.038m	4.270ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.058m	3.414ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.031m	5.880ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.031m	5.880ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.847m	3.396ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.868m	2.541ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.988m	3.116ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.262m	3.102ms	1	1	100.00
		chip_tap_straps_testunlock0	6.699m	7.043ms	1	1	100.00
		chip_tap_straps_rma	4.148m	4.608ms	1	1	100.00
		chip_tap_straps_prod	1.505m	2.954ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.014m	2.608ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.015m	8.312ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.207m	6.646ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.207m	6.646ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.469m	7.800ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	44.623m	24.575ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.436m	4.609ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.000m	5.459ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.669m	18.771ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.353m	2.683ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.308m	5.527ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.299m	3.278ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.099m	9.081ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.580m	2.254ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.493m	4.521ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.791m	2.659ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.041m	2.633ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.109m	6.961ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.575m	5.023ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.809m	2.517ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.575m	5.023ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.537m	2.807ms	1	1	100.00
		chip_sw_aes_smoketest	2.356m	2.877ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.293m	2.593ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.095m	3.050ms	1	1	100.00
		chip_sw_csrng_smoketest	1.956m	2.141ms	1	1	100.00
		chip_sw_entropy_src_smoketest	15.821m	7.230ms	1	1	100.00
		chip_sw_gpio_smoketest	3.400m	2.846ms	1	1	100.00
		chip_sw_hmac_smoketest	3.685m	3.277ms	1	1	100.00
		chip_sw_kmac_smoketest	3.333m	3.399ms	1	1	100.00
		chip_sw_otbn_smoketest	15.247m	7.547ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.804m	5.386ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	2.811m	5.125ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.510m	3.478ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.326m	3.129ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.871m	3.437ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.267m	2.539ms	1	1	100.00
		chip_sw_uart_smoketest	1.969m	2.821ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.030m	2.271ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.343m	4.674ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.127h	62.062ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	44.099m	15.249ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.453m	4.870ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.683m	3.149ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.355m	3.489ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.041h	54.030ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.099h	57.094ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.014m	2.271ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.014m	2.271ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.158h	37.338ms	1	1	100.00
		chip_same_csr_outstanding	40.410m	29.855ms	1	1	100.00
		chip_csr_hw_reset	2.725m	5.206ms	1	1	100.00
		chip_csr_rw	5.354m	5.698ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.158h	37.338ms	1	1	100.00
		chip_same_csr_outstanding	40.410m	29.855ms	1	1	100.00
		chip_csr_hw_reset	2.725m	5.206ms	1	1	100.00
		chip_csr_rw	5.354m	5.698ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	8.410s	262.212us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.000s	54.445us	1	1	100.00
		xbar_smoke_large_delays	52.510s	8.757ms	1	1	100.00
		xbar_smoke_slow_rsp	39.790s	4.436ms	1	1	100.00
		xbar_random_zero_delays	28.110s	440.408us	1	1	100.00
		xbar_random_large_delays	38.920s	5.263ms	1	1	100.00
		xbar_random_slow_rsp	4.567m	33.720ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.830s	72.347us	1	1	100.00
		xbar_error_and_unmapped_addr	28.460s	1.220ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	16.590s	786.089us	1	1	100.00
		xbar_error_and_unmapped_addr	28.460s	1.220ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	37.930s	869.079us	1	1	100.00
		xbar_access_same_device_slow_rsp	11.764m	80.006ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.550s	884.779us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.111m	1.450ms	1	1	100.00
		xbar_stress_all_with_error	1.355m	3.671ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.353m	4.537ms	1	1	100.00
		xbar_stress_all_with_reset_error	14.590s	104.332us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	44.099m	15.249ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.853m	29.523ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.002m	15.499ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.195m	13.599ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	46.138m	16.114ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	45.149m	15.733ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.462m	15.841ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.640m	14.630ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	22.690s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.730s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.480s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.870s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	21.890s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	19.940s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.970s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.070s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.830s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.730s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.720s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	19.690s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.200s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.790s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.360s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.890s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.820s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.660s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.390s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.090s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.570s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.300s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.920s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.090s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.520s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.527m	11.517ms	1	1	100.00
		rom_e2e_asm_init_dev	40.396m	15.488ms	1	1	100.00
		rom_e2e_asm_init_prod	41.459m	16.377ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.210m	16.046ms	1	1	100.00
		rom_e2e_asm_init_rma	40.562m	16.545ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	40.597m	15.223ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.105m	15.282ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.557m	15.643ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.985m	17.738ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	56.874m	34.123ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	56.874m	34.123ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.919m	2.654ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.353m	2.683ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.378m	2.301ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.582m	2.528ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	26.042m	12.432ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.726m	2.876ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.103m	4.398ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.087m	5.435ms	1	1	100.00
		chip_plic_all_irqs_10	4.101m	3.983ms	1	1	100.00
		chip_plic_all_irqs_20	6.443m	4.061ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.404m	2.914ms	0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.808m	12.349ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	6.024m	5.070ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.833m	3.389ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.490m	7.054ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.941m	7.776ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.977m	7.602ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.405h	255.198ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.660m	4.626ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.804m	5.386ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.660m	4.626ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.065m	9.404ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.065m	9.404ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.193m	7.406ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.732m	5.297ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.061m	5.965ms	1	1	100.00
		chip_sw_aes_idle	2.582m	2.528ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.206m	3.183ms	1	1	100.00
		chip_sw_kmac_idle	2.972m	3.362ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.572m	4.231ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.921m	4.751ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	2.891m	3.466ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.718m	4.635ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.179m	9.079ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.906m	3.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.822m	4.058ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.756m	4.001ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.921m	4.368ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.006m	4.359ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.976m	5.272ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.469m	7.800ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.222m	12.184ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.756m	4.001ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.921m	4.368ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.436m	4.609ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.000m	5.459ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.669m	18.771ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.353m	2.683ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.308m	5.527ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.299m	3.278ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.099m	9.081ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.580m	2.254ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.493m	4.521ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.791m	2.659ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.415m	2.780ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.391m	4.857ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.655m	7.251ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.284m	24.751ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.546m	2.583ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.651m	3.309ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.768m	7.795ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.480m	2.671ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.644m	5.015ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.877m	22.903ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.381h	197.424ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.469m	7.800ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.108m	4.315ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.255m	3.441ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.490m	7.054ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.188m	7.471ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.162m	3.953ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.052m	6.033ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.075m	2.851ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	53.072m	18.323ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.226m	2.637ms	1	1	100.00
		chip_sw_edn_entropy_reqs	14.187m	7.564ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.226m	2.637ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.188m	7.471ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.666m	2.919ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.945m	15.778ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	11.268m	5.773ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.000m	5.459ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.979m	3.315ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.436m	4.609ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.079h	43.898ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.945m	15.778ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.192m	3.040ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.079h	43.898ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.792m	14.078ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.467m	4.808ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.095m	5.157ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.095m	5.157ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.727m	2.758ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.299m	3.278ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.206m	3.183ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.514m	3.544ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.575m	3.136ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.341m	4.556ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.122m	5.441ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.345m	4.558ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.356m	4.153ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	15.099m	9.081ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	26.479m	11.986ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	26.042m	12.432ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.971m	13.865ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.166m	3.096ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.513m	2.614ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.580m	2.254ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.276m	3.363ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.083m	7.549ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.972m	3.362ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.103m	4.398ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.262m	3.102ms	1	1	100.00
		chip_tap_straps_rma	4.148m	4.608ms	1	1	100.00
		chip_tap_straps_prod	1.505m	2.954ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.097m	2.857ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	26.527m	11.599ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.357m	4.520ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.079h	43.898ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.644m	3.072ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.858m	6.344ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.464m	7.161ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.225m	6.566ms	0	1	0.00
		chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.955m	9.082ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.342m	7.893ms	1	1	100.00
		chip_prim_tl_access	5.792m	14.078ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.222m	12.184ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.906m	3.666ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.822m	4.058ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.756m	4.001ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.921m	4.368ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.006m	4.359ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.976m	5.272ms	1	1	100.00
		chip_tap_straps_dev	1.262m	3.102ms	1	1	100.00
		chip_tap_straps_rma	4.148m	4.608ms	1	1	100.00
		chip_tap_straps_prod	1.505m	2.954ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.340m	3.553ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.104m	3.641ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.697m	3.288ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.389m	2.978ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.252m	4.021ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.936m	24.036ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.340m	3.553ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.161h	47.357ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.116h	50.201ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.458m	9.848ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.117h	45.240ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.936m	24.036ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.049m	2.862ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.084m	2.789ms	1	1	100.00
		rom_volatile_raw_unlock	59.300s	2.169ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.051m	17.060ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	59.669m	18.771ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.061m	5.965ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.061m	5.965ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.061m	5.965ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.593m	3.597ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.945m	15.778ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.593m	3.597ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.546m	4.867ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.940m	3.318ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.945m	15.778ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.593m	3.597ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.339m	7.717ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.546m	4.867ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.940m	3.318ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.208m	4.005ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.097m	2.857ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.644m	3.072ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.858m	6.344ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.464m	7.161ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.225m	6.566ms	0	1	0.00
		chip_sw_lc_ctrl_transition	4.532m	4.816ms	1	1	100.00
		chip_prim_tl_access	5.792m	14.078ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.792m	14.078ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	20.135m	9.593ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.056m	5.840ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.721m	27.163ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.952m	7.292ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	8.373m	9.746ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.093m	5.631ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.286m	22.497ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.117m	16.162ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.065m	9.404ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.763m	11.634ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.541m	4.139ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.056m	5.840ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.744m	4.842ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.984m	40.817ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.743m	5.886ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.245m	4.498ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.355m	23.703ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.207m	6.467ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.072m	12.428ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	27.324m	29.698ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.630m	2.978ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.955m	9.082ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.955m	9.082ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.072m	12.428ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.355m	23.703ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.541m	4.139ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.804m	5.386ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.451m	4.090ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.181m	5.235ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.269m	4.005ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.808m	12.349ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.279m	2.348ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.941m	7.776ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.842m	4.680ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.680m	4.932ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.211m	3.121ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.940m	3.318ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.181m	5.235ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.181m	5.235ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	20.338m	17.240ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.278m	13.095ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.451m	4.090ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.913m	5.614ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.438m	6.950ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.148m	4.608ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.340m	3.553ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.087m	5.435ms	1	1	100.00
		chip_plic_all_irqs_10	4.101m	3.983ms	1	1	100.00
		chip_plic_all_irqs_20	6.443m	4.061ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.714m	3.507ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.762m	3.447ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	44.099m	15.249ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.521m	7.136ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.865m	3.768ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.330m	3.836ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.272m	2.474ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.546m	4.867ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.493m	4.521ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	8.543m	7.969ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.075m	8.066ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.342m	7.893ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.207m	6.646ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.207m	6.467ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.561m	24.544ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.635m	3.112ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.323m	4.167ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.510m	4.799ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.561m	24.544ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.561m	24.544ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.858m	12.594ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.858m	12.594ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.742m	5.440ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	56.874m	34.123ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.346m	2.775ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.979m	3.221ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.680m	4.044ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.910m	3.790ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.587m	8.400ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.476h	31.663ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.483m	12.526ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.661m	2.729ms	1	1	100.00
V2		TOTAL			234	275	85.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.428m	3.230ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.845m	3.240ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.644h	71.835ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.765m	3.787ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.898m	11.011ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.623m	11.340ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.253m	10.728ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.107m	3.761ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.182m	5.253ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.004m	4.746ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	16.414s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.280m	5.210ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.054m	2.935ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.053m	7.125ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	11.313m	5.854ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.587m	2.809ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.798m	5.223ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	49.490s	2.177ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.305m	4.902ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.067m	6.550ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.927m	5.067ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.072m	12.428ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.898m	11.011ms	1	1	100.00
		rom_e2e_jtag_debug_dev	20.623m	11.340ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.253m	10.728ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.675m	4.719ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.887m	5.580ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.516h	38.132ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.516h	38.132ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.534m	3.309ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.105m	4.242ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.648m	18.186ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.869m	2.946ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	7.119m	5.812ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	33.940m	22.612ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.289m	2.810ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.305m	3.196ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.124m	3.395ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.600s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.219m	2.958ms	1	1	100.00
		TOTAL			280	326	85.89

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.110864643311784881079124570713486859835738396543141495789190632644452340851244
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.59488219998647302775094896256283863576991413710274559540640314343750339738506
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.109911219173039687283514885594369782791425902039492929250863796224204376658223
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.74715864276921752913249396595903869047624721766445086679569392761013742466395
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.71083954384411792334097232642513315082890441134207034817317631670281210910193
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.108888488242740213584975358692217899260087419808458623968368380603836019051931
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.5444384874457651751319826054232998658632150990657599594623527254685907718410
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.45921073297371763207344913626404677950937110478067911614486690036380118225589
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.69903215725222527181735379523061176623556319897811788663589487097198352355811
    Line 495, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.25907640168196045706658571926220359933517984454269514312870746045114631694245
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.81128595733461012653221762475218015667304530096305251581078870709599157266535
    Line 560, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4769267248567873568902556685461996285870215784038509017337851160264559760339
    Line 542, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.53467548222730966558838068093501224217684930612926747362198407407582452847418
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.114725808390631398151823772679251984904153799651290175669525566102047332903557
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.176s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.30692305535067461305128274002047062367832438719230057029821801549073296069285
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.167s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.25094228501329145408169222103451881105347874457831504604718000240118285468897
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.77083146847201602041614495435100291180509519600882741594975797858533242208373
    Line 471, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.106466427487895054449662609154500781494962934878311498391501157621260226925985
    Line 513, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.65098293293155857105936930769489247376667881750975879167494674767420626269791
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.30379868012746365797174835253197321044261313254706612143591448978609349201761
    Line 636, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3395.553500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3395.553500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.104422143070326542994613016264488260189588729403892993072984855532903012034705
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3768.446024 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3768.446024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.101667048773913712812912020979264897473609578672904726022969297225163427253069
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6565.508216 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6565.508216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.32557105534265281933966345926165685449405794046575257140918488848575478104917
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22611.914469 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22611.914469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115762) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.21885265954023369082826694894442029948537188484490281862345389280957160516218
Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5234.581776 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115762) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5234.581776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.67132758936245666697438211162314941372334027850563995866516011809671735895551
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 12593.508472 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 12593.508472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.104376988428970600416709758090601811245592482450415209508947234088383404076999
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34123.182556 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34123.182556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.80911094521177666154209196155127230897007462836015556071153617844260940500270
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2875.867194 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2875.867194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.38186222956038836663954618779193309789570912313154245380871552268479776865553
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3389.193920 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3389.193920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.73933704679618345754335957846343964106816328238775010896769049102550472304902
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_alert_handler_entropy has 1 failures.
  - 0.chip_sw_alert_handler_entropy.3943561746749987254850455191739703832699429178760515468299086363308628075892
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log
```
  UVM_ERROR @ 2913.520712 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 2913.520712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.84775939637622392004525778112016871103755210772952977460994674105319670902281
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3543.909763 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3543.909763 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42264) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.9310425688708781987808830492809556516001343225238825616903249173673002838933
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2270.998855 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@42264) { a_addr: 'h10524  a_data: 'h1e2f24a8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h186bd  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2270.998855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.64979590918541991148993528583772236000236867489842252235705584850986444940086
    Line 218, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 3552.580539 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10768 read out mismatch
  UVM_INFO @ 3552.580539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.41746319901692125986503481103430774012358560935190758649388292614942149004590
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3148.944000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3148.944000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.2536831775016698165101771899373207619261355778908304009613403446373841598759
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3489.304000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3489.304000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.44011760167512781685784534947019918580068323714390982627105146057833416614890
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 24575.196855 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 24575.196855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.103316527856347113922958737134519254037418926193894118744600068992354332305822
    Line 462, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3787.077394 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3787.077394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.76636514171404337782121352548943613124670580452890135625798289602406815322255
    Line 532, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.31085831568636108086648555982521267848039728409732123599417054805339876748211
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32974) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.106375355725092641023044089619520830577762013533763657832318810830670787041540
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2379.728672 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32974) { a_addr: 'h10468  a_data: 'h8e3bb2a5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1b12d  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2379.728672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---