ADC_CTRL Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.220s	6.130ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.210s	844.830us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.440s	313.504us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.147m	26.557ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.520s	1.094ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.540s	317.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.440s	313.504us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	1.094ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.046m	164.360ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	54.640s	498.797ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.486m	332.099ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.884m	327.200ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.846m	204.223ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.898m	600.372ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.277m	168.042ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.011m	189.124ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.060s	3.817ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	56.380s	32.223ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.328m	91.382ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.062m	496.224ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.150s	326.974us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.170s	522.961us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.850s	656.725us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.850s	656.725us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.210s	844.830us	1	1	100.00
		adc_ctrl_csr_rw	1.440s	313.504us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	1.094ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.150s	3.029ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.210s	844.830us	1	1	100.00
		adc_ctrl_csr_rw	1.440s	313.504us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	1.094ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.150s	3.029ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	12.130s	4.193ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.630s	8.840ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.630s	8.840ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.270s	1.942ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00