EDN Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.930s 35.745us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.970s 16.862us 1 1 100.00
V1 csr_rw edn_csr_rw 0.860s 19.565us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.800s 139.020us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.140s 25.445us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.300s 116.760us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.860s 19.565us 1 1 100.00
edn_csr_aliasing 1.140s 25.445us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.740s 123.800us 1 1 100.00
V2 csrng_commands edn_genbits 1.740s 123.800us 1 1 100.00
V2 genbits edn_genbits 1.740s 123.800us 1 1 100.00
V2 interrupts edn_intr 0.900s 25.901us 1 1 100.00
V2 alerts edn_alert 1.250s 31.219us 1 1 100.00
V2 errs edn_err 1.130s 33.403us 1 1 100.00
V2 disable edn_disable 1.010s 30.316us 1 1 100.00
edn_disable_auto_req_mode 1.030s 101.522us 1 1 100.00
V2 stress_all edn_stress_all 2.130s 204.238us 1 1 100.00
V2 intr_test edn_intr_test 0.900s 50.703us 1 1 100.00
V2 alert_test edn_alert_test 0.880s 23.197us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.130s 645.107us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.130s 645.107us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.970s 16.862us 1 1 100.00
edn_csr_rw 0.860s 19.565us 1 1 100.00
edn_csr_aliasing 1.140s 25.445us 1 1 100.00
edn_same_csr_outstanding 1.300s 133.038us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.970s 16.862us 1 1 100.00
edn_csr_rw 0.860s 19.565us 1 1 100.00
edn_csr_aliasing 1.140s 25.445us 1 1 100.00
edn_same_csr_outstanding 1.300s 133.038us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.030s 1.134ms 1 1 100.00
edn_tl_intg_err 2.490s 1.371ms 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.010s 16.208us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.250s 31.219us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.030s 1.134ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.030s 1.134ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.030s 1.134ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.030s 1.134ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.250s 31.219us 1 1 100.00
edn_sec_cm 6.030s 1.134ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.250s 31.219us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.490s 1.371ms 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets