HMAC Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.600s 1.222ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.730s 22.808us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.800s 33.519us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.790s 1.280ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.400s 316.918us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.430s 162.991us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.800s 33.519us 1 1 100.00
hmac_csr_aliasing 5.400s 316.918us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.090s 366.354us 1 1 100.00
V2 back_pressure hmac_back_pressure 31.850s 1.670ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.857m 5.830ms 1 1 100.00
hmac_test_sha384_vectors 18.110s 228.935us 1 1 100.00
hmac_test_sha512_vectors 6.465m 44.483ms 1 1 100.00
hmac_test_hmac256_vectors 7.190s 253.867us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 660.117us 1 1 100.00
hmac_test_hmac512_vectors 8.830s 520.865us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.110s 1.944ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 12.808m 5.561ms 1 1 100.00
V2 error hmac_error 57.510s 2.920ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.026m 1.686ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.600s 1.222ms 1 1 100.00
hmac_long_msg 15.090s 366.354us 1 1 100.00
hmac_back_pressure 31.850s 1.670ms 1 1 100.00
hmac_datapath_stress 12.808m 5.561ms 1 1 100.00
hmac_burst_wr 17.110s 1.944ms 1 1 100.00
hmac_stress_all 2.236m 13.188ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.600s 1.222ms 1 1 100.00
hmac_long_msg 15.090s 366.354us 1 1 100.00
hmac_back_pressure 31.850s 1.670ms 1 1 100.00
hmac_datapath_stress 12.808m 5.561ms 1 1 100.00
hmac_wipe_secret 1.026m 1.686ms 1 1 100.00
hmac_test_sha256_vectors 2.857m 5.830ms 1 1 100.00
hmac_test_sha384_vectors 18.110s 228.935us 1 1 100.00
hmac_test_sha512_vectors 6.465m 44.483ms 1 1 100.00
hmac_test_hmac256_vectors 7.190s 253.867us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 660.117us 1 1 100.00
hmac_test_hmac512_vectors 8.830s 520.865us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.600s 1.222ms 1 1 100.00
hmac_long_msg 15.090s 366.354us 1 1 100.00
hmac_back_pressure 31.850s 1.670ms 1 1 100.00
hmac_datapath_stress 12.808m 5.561ms 1 1 100.00
hmac_burst_wr 17.110s 1.944ms 1 1 100.00
hmac_error 57.510s 2.920ms 1 1 100.00
hmac_wipe_secret 1.026m 1.686ms 1 1 100.00
hmac_test_sha256_vectors 2.857m 5.830ms 1 1 100.00
hmac_test_sha384_vectors 18.110s 228.935us 1 1 100.00
hmac_test_sha512_vectors 6.465m 44.483ms 1 1 100.00
hmac_test_hmac256_vectors 7.190s 253.867us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 660.117us 1 1 100.00
hmac_test_hmac512_vectors 8.830s 520.865us 1 1 100.00
hmac_stress_all 2.236m 13.188ms 1 1 100.00
V2 stress_all hmac_stress_all 2.236m 13.188ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 68.823us 1 1 100.00
V2 intr_test hmac_intr_test 0.610s 26.471us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.710s 49.561us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.710s 49.561us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.730s 22.808us 1 1 100.00
hmac_csr_rw 0.800s 33.519us 1 1 100.00
hmac_csr_aliasing 5.400s 316.918us 1 1 100.00
hmac_same_csr_outstanding 0.940s 20.554us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.730s 22.808us 1 1 100.00
hmac_csr_rw 0.800s 33.519us 1 1 100.00
hmac_csr_aliasing 5.400s 316.918us 1 1 100.00
hmac_same_csr_outstanding 0.940s 20.554us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.830s 67.465us 1 1 100.00
hmac_tl_intg_err 3.080s 247.017us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.080s 247.017us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.600s 1.222ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.530s 129.979us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.387m 84.349ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.290s 74.971us 1 1 100.00
TOTAL 28 28 100.00