I2C Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.860s	1.589ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	22.030s	8.901ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.700s	35.951us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.840s	23.048us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.270s	1.057ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.040s	84.374us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.940s	69.588us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.840s	23.048us	1	1	100.00
		i2c_csr_aliasing	1.040s	84.374us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.290s	1.545ms	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.676m	35.131ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	12.050s	8.206ms	1	1	100.00
V2	host_override	i2c_host_override	0.690s	26.458us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	52.180s	19.110ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	57.570s	2.692ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.970s	123.038us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.540s	786.593us	1	1	100.00
		i2c_host_fifo_reset_rx	6.730s	192.099us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	40.150s	2.434ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.230s	3.510ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.930s	328.218us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.080s	2.110ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	2.429m	22.228ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.480s	1.698ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	3.900s	751.389us	1	1	100.00
		i2c_target_intr_smoke	5.000s	2.466ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.860s	139.391us	1	1	100.00
		i2c_target_fifo_reset_tx	1.180s	221.087us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.967m	40.988ms	1	1	100.00
		i2c_target_stress_rd	3.900s	751.389us	1	1	100.00
		i2c_target_intr_stress_wr	1.606m	22.901ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.300s	13.376ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	15.760s	2.958ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.320s	2.355ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	12.190s	10.023ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.180s	852.614us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.050s	329.764us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	12.050s	8.206ms	1	1	100.00
		i2c_host_perf_precise	1.180s	92.710us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.230s	3.510ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.210s	107.791us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.510s	4.569ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.780s	2.058ms	1	1	100.00
		i2c_target_nack_txstretch	1.240s	152.107us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.510s	257.201us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.090s	602.243us	1	1	100.00
V2	alert_test	i2c_alert_test	0.630s	17.351us	1	1	100.00
V2	intr_test	i2c_intr_test	0.820s	17.609us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.260s	155.492us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.260s	155.492us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.700s	35.951us	1	1	100.00
		i2c_csr_rw	0.840s	23.048us	1	1	100.00
		i2c_csr_aliasing	1.040s	84.374us	1	1	100.00
		i2c_same_csr_outstanding	0.960s	22.431us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.700s	35.951us	1	1	100.00
		i2c_csr_rw	0.840s	23.048us	1	1	100.00
		i2c_csr_aliasing	1.040s	84.374us	1	1	100.00
		i2c_same_csr_outstanding	0.960s	22.431us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.930s	90.085us	1	1	100.00
		i2c_sec_cm	0.870s	42.682us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.930s	90.085us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.260s	211.753us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.580s	123.913us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.510s	1.035ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.43006921869699073042507811348586679377780820442253053305720107785439067333181
      Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 1544668030 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1544668030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.103646495637485789600845604673245196373807493837484609243090998308889368431998
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 35131495057 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 35131495057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.43415372535183831264265687131922702038156118253951075779514010072763084631539
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 211752594 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 211752594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.2433423526414217719816740491833492712918747560081742725482107994772536251740
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1034890248 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1034890248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.113153299486116120754352703108760188517921900275050107460660810566365611213390
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2110398470 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2110398470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.94550794734014803969651525717537651268430061751501847199616549581512460184854
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 123913446 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 123913446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.92480681079877030549878692701030084401237393797049609114396362167339988854767
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10022954220 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10022954220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.76728165118694128846708542756022762080173287569144392164564406977865545953626
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 328218315 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @23820