KEYMGR Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.880s 92.289us 1 1 100.00
V1 random keymgr_random 5.740s 1.388ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.320s 35.933us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.240s 100.748us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 14.530s 9.161ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 3.750s 2.286ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.460s 90.905us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.240s 100.748us 1 1 100.00
keymgr_csr_aliasing 3.750s 2.286ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 5.040s 231.678us 1 1 100.00
V2 sideload keymgr_sideload 1.910s 38.728us 1 1 100.00
keymgr_sideload_kmac 2.160s 75.374us 1 1 100.00
keymgr_sideload_aes 2.740s 124.889us 1 1 100.00
keymgr_sideload_otbn 2.130s 136.290us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.770s 29.154us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.070s 35.694us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 3.200s 469.981us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 5.220s 571.997us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 6.100s 2.253ms 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.580s 140.524us 1 1 100.00
V2 stress_all keymgr_stress_all 4.690s 234.280us 1 1 100.00
V2 intr_test keymgr_intr_test 0.730s 94.171us 1 1 100.00
V2 alert_test keymgr_alert_test 0.750s 127.544us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 3.890s 148.607us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 3.890s 148.607us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.320s 35.933us 1 1 100.00
keymgr_csr_rw 1.240s 100.748us 1 1 100.00
keymgr_csr_aliasing 3.750s 2.286ms 1 1 100.00
keymgr_same_csr_outstanding 2.190s 364.269us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.320s 35.933us 1 1 100.00
keymgr_csr_rw 1.240s 100.748us 1 1 100.00
keymgr_csr_aliasing 3.750s 2.286ms 1 1 100.00
keymgr_same_csr_outstanding 2.190s 364.269us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 5.500s 480.843us 1 1 100.00
keymgr_tl_intg_err 6.910s 1.081ms 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.790s 193.879us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.790s 193.879us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.790s 193.879us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.790s 193.879us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 7.030s 434.058us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 6.910s 1.081ms 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.790s 193.879us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 5.040s 231.678us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 5.740s 1.388ms 1 1 100.00
keymgr_csr_rw 1.240s 100.748us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 5.740s 1.388ms 1 1 100.00
keymgr_csr_rw 1.240s 100.748us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 5.740s 1.388ms 1 1 100.00
keymgr_csr_rw 1.240s 100.748us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.070s 35.694us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 6.100s 2.253ms 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 6.100s 2.253ms 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 5.740s 1.388ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 3.700s 308.896us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.690s 153.669us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.070s 35.694us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.690s 153.669us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.690s 153.669us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.690s 153.669us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 5.500s 480.843us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.690s 153.669us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 7.870s 1.296ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00