| V1 |
smoke |
kmac_smoke |
4.890s |
1.204ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.960s |
66.541us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.390s |
18.299us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
8.500s |
4.011ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
4.030s |
246.858us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.810s |
101.840us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.390s |
18.299us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.030s |
246.858us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.900s |
32.108us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.480s |
38.220us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
12.445m |
35.581ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
12.130s |
169.963us |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
30.780s |
7.522ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
32.273m |
171.823ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.020s |
1.815ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
18.438m |
186.960ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
28.923m |
60.668ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
4.718m |
17.313ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.450s |
190.532us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.260s |
88.308us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
5.273m |
99.834ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
4.630m |
32.175ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
18.470s |
4.522ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
2.874m |
12.946ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
2.295m |
8.900ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
6.970s |
2.252ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
2.930s |
211.859us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.320s |
25.826us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.260s |
25.696us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
33.530s |
4.852ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.340s |
50.270us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
44.350s |
1.767ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.840s |
50.943us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.190s |
53.443us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.700s |
66.425us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.700s |
66.425us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.960s |
66.541us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.390s |
18.299us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.030s |
246.858us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.290s |
92.428us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.960s |
66.541us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.390s |
18.299us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
4.030s |
246.858us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.290s |
92.428us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.800s |
76.099us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.800s |
76.099us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.800s |
76.099us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.800s |
76.099us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
4.200s |
395.507us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.331m |
33.333ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
4.100s |
316.303us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
4.100s |
316.303us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.340s |
50.270us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
4.890s |
1.204ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
5.273m |
99.834ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.800s |
76.099us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.331m |
33.333ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.331m |
33.333ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.331m |
33.333ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
4.890s |
1.204ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.340s |
50.270us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.331m |
33.333ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
45.300s |
8.625ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
4.890s |
1.204ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.750m |
19.361ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |