PATTGEN Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.000s	138.225us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	104.635us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	76.774us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	315.638us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	26.675us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	43.062us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	76.774us	1	1	100.00
		pattgen_csr_aliasing	2.000s	26.675us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	35.517m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	12.000s	3.772ms	1	1	100.00
V2	error	pattgen_error	1.000s	30.313us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.181h	1.683s	0	1	0.00
V2	alert_test	pattgen_alert_test	1.000s	13.513us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	12.256us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	482.338us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	482.338us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	104.635us	1	1	100.00
		pattgen_csr_rw	2.000s	76.774us	1	1	100.00
		pattgen_csr_aliasing	2.000s	26.675us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	47.134us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	104.635us	1	1	100.00
		pattgen_csr_rw	2.000s	76.774us	1	1	100.00
		pattgen_csr_aliasing	2.000s	26.675us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	47.134us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	533.530us	1	1	100.00
		pattgen_sec_cm	2.000s	40.371us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	533.530us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	53.000s	7.525ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.000s	54.237us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.54880967665817421786101493638890242358114706099923327183216669006214840921377
      Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.13770169645352671194649909902159074747842908795798513329503397576087377112408
      Line 145, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1319142662 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1319160523 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1319160523 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 1319493856 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.11825121136723604765424071540169917665314887147303365989313484926084355384133
      Line 131, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @  82433257 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
        --> channel 0 item mismatch!
        --> EXP:
        ------------------------------------
        Name      Type          Size  Value