SPI_DEVICE/1R1W Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.776m	12.672ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	207.257us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.250s	121.868us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	7.830s	374.274us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.500s	1.127ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.580s	66.092us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.250s	121.868us	1	1	100.00
		spi_device_csr_aliasing	5.500s	1.127ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.650s	13.649us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.250s	54.908us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.870s	64.698us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.920s	1.890us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.710s	4.645us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.480s	348.904us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.480s	348.904us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.370s	8.978ms	1	1	100.00
		spi_device_tpm_sts_read	0.980s	128.421us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.490s	3.392ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.950s	245.781us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	11.120s	4.903ms	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	11.120s	4.903ms	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.670s	716.879us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.670s	716.879us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.670s	716.879us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.670s	716.879us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.670s	716.879us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.460s	369.024us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.910s	754.874us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.910s	754.874us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.910s	754.874us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.990s	331.856us	1	1	100.00
		spi_device_read_buffer_direct	3.560s	454.846us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.910s	754.874us	1	1	100.00
		spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	40.210s	13.161ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	1.710s	33.380us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	1.710s	33.380us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.776m	12.672ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	27.280s	11.092ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.174m	29.242ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.680s	16.851us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.810s	12.351us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.360s	422.718us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.360s	422.718us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	207.257us	1	1	100.00
		spi_device_csr_rw	2.250s	121.868us	1	1	100.00
		spi_device_csr_aliasing	5.500s	1.127ms	1	1	100.00
		spi_device_same_csr_outstanding	1.570s	27.296us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	207.257us	1	1	100.00
		spi_device_csr_rw	2.250s	121.868us	1	1	100.00
		spi_device_csr_aliasing	5.500s	1.127ms	1	1	100.00
		spi_device_same_csr_outstanding	1.570s	27.296us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.950s	76.547us	1	1	100.00
		spi_device_tl_intg_err	16.000s	2.169ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.000s	2.169ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	34.940s	2.595ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.85989957216490807822324378400958181056829781999852480608287878294686244386678
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1080425 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[97])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1080425 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1080425 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.87351151336232933832501029094241085641903470912232411855532291338829684678445
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1919982 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e88c5 [1111101000100011000101] vs 0x0 [0])
        UVM_ERROR @   1968982 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x22c1f4 [1000101100000111110100] vs 0x0 [0])
        UVM_ERROR @   2000982 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2655d1 [1001100101010111010001] vs 0x0 [0])
        UVM_ERROR @   2082982 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf4d874 [111101001101100001110100] vs 0x0 [0])
        UVM_ERROR @   2181982 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x59ffdc [10110011111111111011100] vs 0x0 [0])