SPI_DEVICE/2P Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.540m	148.764ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.190s	287.661us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.760s	30.027us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.610s	1.843ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.240s	1.094ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.000s	66.456us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.760s	30.027us	1	1	100.00
		spi_device_csr_aliasing	16.240s	1.094ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	13.069us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.160s	65.420us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.980s	14.619us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	30.648us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	15.119us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.240s	219.700us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.240s	219.700us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	13.270s	7.871ms	1	1	100.00
		spi_device_tpm_sts_read	0.780s	21.132us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.390s	3.298ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.490s	1.195ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.690s	11.071ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.690s	11.071ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.560s	1.227ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.560s	1.227ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.560s	1.227ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.560s	1.227ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.560s	1.227ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.100s	728.878us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	25.720s	15.397ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	25.720s	15.397ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	25.720s	15.397ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.800s	2.559ms	1	1	100.00
		spi_device_read_buffer_direct	8.300s	1.471ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	25.720s	15.397ms	1	1	100.00
		spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.040m	329.071ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.260s	1.485ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.260s	1.485ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.540m	148.764ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.758m	189.791ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.191m	11.092ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.760s	92.973us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.880s	14.511us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.490s	106.261us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.490s	106.261us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.190s	287.661us	1	1	100.00
		spi_device_csr_rw	1.760s	30.027us	1	1	100.00
		spi_device_csr_aliasing	16.240s	1.094ms	1	1	100.00
		spi_device_same_csr_outstanding	3.300s	408.029us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.190s	287.661us	1	1	100.00
		spi_device_csr_rw	1.760s	30.027us	1	1	100.00
		spi_device_csr_aliasing	16.240s	1.094ms	1	1	100.00
		spi_device_same_csr_outstanding	3.300s	408.029us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.060s	118.316us	1	1	100.00
		spi_device_tl_intg_err	5.720s	285.500us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.720s	285.500us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	46.130s	22.423ms	1	1	100.00
		TOTAL			33	33	100.00