SPI_HOST Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	51.000s	29.658ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	7.000s	192.745us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	7.000s	45.739us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	8.000s	64.331us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	6.000s	33.746us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	46.324us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	7.000s	45.739us	1	1	100.00
		spi_host_csr_aliasing	6.000s	33.746us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	7.000s	17.680us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	7.000s	24.316us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	56.777us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	351.398us	1	1	100.00
		spi_host_error_cmd	1.000s	24.250us	1	1	100.00
		spi_host_event	8.000s	996.938us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	198.420us	1	1	100.00
V2	speed	spi_host_speed	3.000s	198.420us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	198.420us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	403.092us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	122.908us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	198.420us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	198.420us	1	1	100.00
V2	duplex	spi_host_smoke	51.000s	29.658ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	51.000s	29.658ms	1	1	100.00
V2	stress_all	spi_host_stress_all	41.000s	4.158ms	1	1	100.00
V2	spien	spi_host_spien	3.000s	384.474us	1	1	100.00
V2	stall	spi_host_status_stall	14.000s	6.533ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	694.612us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	351.398us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	17.849us	1	1	100.00
V2	intr_test	spi_host_intr_test	8.000s	23.312us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	10.000s	156.198us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	10.000s	156.198us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	7.000s	192.745us	1	1	100.00
		spi_host_csr_rw	7.000s	45.739us	1	1	100.00
		spi_host_csr_aliasing	6.000s	33.746us	1	1	100.00
		spi_host_same_csr_outstanding	6.000s	70.372us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	7.000s	192.745us	1	1	100.00
		spi_host_csr_rw	7.000s	45.739us	1	1	100.00
		spi_host_csr_aliasing	6.000s	33.746us	1	1	100.00
		spi_host_same_csr_outstanding	6.000s	70.372us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	9.000s	135.182us	1	1	100.00
		spi_host_sec_cm	2.000s	252.694us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	9.000s	135.182us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.000m	10.136ms	1	1	100.00
		TOTAL			26	26	100.00