SRAM_CTRL/MAIN Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.130s	1.852ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	43.704us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.910s	82.135us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.230s	141.690us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.900s	20.083us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.910s	728.249us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.910s	82.135us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	20.083us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.853m	2.744ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.037m	11.185ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.887m	11.950ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.534m	12.198ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.324m	781.752ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.715m	10.337ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.630s	12.601ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.051m	13.801ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.150s	2.567ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.573m	11.809ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	43.280s	3.153ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.090s	745.899us	1	1	100.00
		sram_ctrl_throughput_w_readback	42.160s	913.136us	1	1	100.00
V2	regwen	sram_ctrl_regwen	2.013m	25.193ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.360s	703.923us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	24.337m	58.327ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.840s	28.935us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.850s	147.676us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.850s	147.676us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	43.704us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	82.135us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	20.083us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	253.478us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	43.704us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	82.135us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	20.083us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	253.478us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.790s	7.196ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
		sram_ctrl_tl_intg_err	2.240s	194.631us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.240s	194.631us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	2.013m	25.193ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	2.013m	25.193ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.910s	82.135us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.051m	13.801ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.051m	13.801ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.051m	13.801ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.630s	12.601ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.970s	1.365ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.790s	7.196ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.060s	2.769ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.130s	1.852ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.130s	1.852ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.051m	13.801ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.630s	12.601ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.130s	1.852ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.760s	938.143ns	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	56.460s	2.740ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.6702546126706288589567151106386226640646813918280612142431660126480080924407
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @    938143 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @    938143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---