SRAM_CTRL/RET Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.820s	1.478ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	77.665us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	76.270us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.500s	408.154us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.840s	17.163us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.110s	32.990us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	76.270us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	17.163us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.720s	541.642us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.510s	97.042us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.788m	78.534ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.903m	11.542ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.210s	1.380ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.006m	2.064ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.880s	699.896us	1	1	100.00
V2	executable	sram_ctrl_executable	4.967m	2.933ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	28.280s	562.519us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.959m	4.428ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.010s	106.022us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	9.070s	101.927us	1	1	100.00
		sram_ctrl_throughput_w_readback	26.920s	234.916us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.546m	75.076ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.940s	43.226us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.350m	77.985ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	22.220us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.150s	408.951us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.150s	408.951us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	77.665us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	76.270us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	17.163us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.780s	41.241us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	77.665us	1	1	100.00
		sram_ctrl_csr_rw	0.740s	76.270us	1	1	100.00
		sram_ctrl_csr_aliasing	0.840s	17.163us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.780s	41.241us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.230s	880.383us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
		sram_ctrl_tl_intg_err	1.220s	115.948us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.220s	115.948us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.546m	75.076ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.546m	75.076ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	76.270us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.967m	2.933ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.967m	2.933ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.967m	2.933ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.880s	699.896us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.100s	34.497us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.230s	880.383us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.330s	119.644us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.820s	1.478ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.820s	1.478ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.967m	2.933ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.880s	699.896us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.820s	1.478ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	13.115us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.014m	1.866ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.14111484324060341254252652927517036327068481721968327841474684624969766648008
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  13115072 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  13115072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---