SYSRST_CTRL Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.660s 2.128ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.490s 2.491ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.360s 2.416ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.860s 2.370ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.420s 4.019ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 1.100s 2.123ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 7.500s 4.172ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.970s 2.610ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.730s 2.078ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.100s 2.123ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.970s 2.610ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 43.380s 81.185ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.513m 78.587ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.220s 3.133ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.000s 4.438ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 5.270s 2.511ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.030s 2.074ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 1.150s 4.200ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.120s 2.621ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.760s 6.541ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 18.070s 38.003ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 13.470s 7.622ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 4.250s 2.011ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.570s 2.056ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.640s 2.075ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.640s 2.075ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.420s 4.019ms 1 1 100.00
sysrst_ctrl_csr_rw 1.100s 2.123ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.970s 2.610ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.040s 5.243ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.420s 4.019ms 1 1 100.00
sysrst_ctrl_csr_rw 1.100s 2.123ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.970s 2.610ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.040s 5.243ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 44.090s 22.011ms 1 1 100.00
sysrst_ctrl_tl_intg_err 11.560s 44.062ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 11.560s 44.062ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 4.140s 8.466ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00