UART Simulation Results

Wednesday October 15 2025 19:22:10 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.890s	692.277us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.770s	54.301us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.610s	37.376us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.780s	168.886us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s	59.065us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.760s	30.966us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.610s	37.376us	1	1	100.00
		uart_csr_aliasing	0.760s	59.065us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	44.970s	76.544ms	1	1	100.00
V2	parity	uart_smoke	1.890s	692.277us	1	1	100.00
		uart_tx_rx	44.970s	76.544ms	1	1	100.00
V2	parity_error	uart_intr	23.890s	57.118ms	1	1	100.00
		uart_rx_parity_err	25.160s	79.675ms	1	1	100.00
V2	watermark	uart_tx_rx	44.970s	76.544ms	1	1	100.00
		uart_intr	23.890s	57.118ms	1	1	100.00
V2	fifo_full	uart_fifo_full	17.140s	29.308ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	43.640s	113.555ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.291m	61.461ms	1	1	100.00
V2	rx_frame_err	uart_intr	23.890s	57.118ms	1	1	100.00
V2	rx_break_err	uart_intr	23.890s	57.118ms	1	1	100.00
V2	rx_timeout	uart_intr	23.890s	57.118ms	1	1	100.00
V2	perf	uart_perf	1.721m	10.079ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.630s	7.552ms	1	1	100.00
V2	line_loopback	uart_loopback	4.630s	7.552ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	9.920s	7.603ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.830s	817.198us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.200s	882.670us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.610s	6.202ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.248m	160.790ms	1	1	100.00
V2	stress_all	uart_stress_all	11.774m	165.044ms	1	1	100.00
V2	alert_test	uart_alert_test	0.860s	44.947us	1	1	100.00
V2	intr_test	uart_intr_test	0.640s	37.500us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.730s	375.690us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.730s	375.690us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.770s	54.301us	1	1	100.00
		uart_csr_rw	0.610s	37.376us	1	1	100.00
		uart_csr_aliasing	0.760s	59.065us	1	1	100.00
		uart_same_csr_outstanding	0.740s	75.903us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.770s	54.301us	1	1	100.00
		uart_csr_rw	0.610s	37.376us	1	1	100.00
		uart_csr_aliasing	0.760s	59.065us	1	1	100.00
		uart_same_csr_outstanding	0.740s	75.903us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.230s	71.250us	1	1	100.00
		uart_tl_intg_err	0.970s	50.499us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.970s	50.499us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	44.740s	2.449ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.61373899093756453563210349236706825310166298111272426230433154718036428599783
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 6235285615 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 6235295819 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 6235306023 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 6241224343 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 6241224343 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0